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UPA1740

更新时间： 2024-02-17 12:45:17
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8页 80K
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UPA1740TP Data Sheet | Data Sheet[05/2002]

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UPA1740 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOT
包装说明：SMALL OUTLINE, R-PDSO-G8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
风险等级：5.76配置：SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：200 V最大漏极电流 (ID)：7 A
最大漏源导通电阻：0.44 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
JESD-30 代码：R-PDSO-G8JESD-609代码：e6
元件数量：1端子数量：8
工作模式：ENHANCEMENT MODE封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260极性/信道类型：N-CHANNEL
认证状态：Not Qualified表面贴装：YES
端子面层：TIN BISMUTH端子形式：GULL WING
端子位置：DUAL处于峰值回流温度下的最长时间：10
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

UPA1740 数据手册

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DATA SHEET  
MOS FIELD EFFECT TRANSISTOR  
µPA1740TP  
SWITCHING  
N-CHANNEL POWER MOS FET  
PACKAGE DRAWING (Unit: mm)  
DESCRIPTION  
The µPA1740TP is N-channel MOS FET device that features a  
low on-state resistance and excellent swiching characteristics, and  
designed for high voltage applications such as DC/DC converter.  
8
5
1, 2, 3  
4
5, 6, 7, 8, 9 : Drain  
: Source  
: Gate  
FEATURES  
• High voltage: VDSS = 200 V  
• Gate voltage rating: ±30 V  
• Low on-state resistance  
6.0 ±0.3  
1
4
0.8 ±0.2  
4.4 ±0.15  
+0.17  
–0.2  
5.2  
S
RDS(on) = 0.44 Ω MAX. (VGS = 10 V, ID = 3.5 A)  
• Low input capacitance  
Ciss = 420 pF TYP. (VDS = 10 V, VGS = 0 V)  
• Built-in gate protection diode  
• Small and surface mount package (Power HSOP8)  
• Avalanche capability rated  
0.10 S  
1.27 TYP.  
+0.10  
–0.05  
0.40  
0.12 M  
1
4
2.0 ±0.2  
9
ORDERING INFORMATION  
4.1 MAX.  
PART NUMBER  
PACKAGE  
µPA1740TP  
Power HSOP8  
8
5
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, Unless otherwise noted, All terminals are connected.)  
Drain to Source Voltage (VGS = 0 V)  
Gate to Source Voltage (VDS = 0 V)  
Drain Current (DC) (TC = 25°C)  
Drain Current (pulse) Note1  
VDSS  
VGSS  
ID(DC)  
ID(pulse)  
PT1  
200  
V
±30  
V
±7.0  
±21  
A
A
EQUIVALENT CIRCUIT  
Total Power Dissipation (TC = 25°C)  
Total Power Dissipation (TA = 25°C)Note2  
Channel Temperature  
22  
W
W
°C  
°C  
A
PT2  
1.0  
Drain  
Tch  
150  
Storage Temperature  
Tstg  
–55 to + 150  
7.0  
Body  
Single Avalanche Current Note3  
Single Avalanche Energy Note3  
Repetitive Avalanche Current Note4  
Repetitive Avalanche Energy Note4  
Diode  
Gate  
IAS  
EAS  
4.9  
mJ  
A
Gate  
IAR  
7.0  
Protection  
Diode  
Source  
EAR  
2.2  
mJ  
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%  
2. Mounted on a glass epoxy board (1 inch x 1 inch x 0.8 mm), PW = 10 sec  
3. Starting Tch = 25°C, VDD = 100 V, RG = 25 Ω, L = 100 µH, VGS = 20 → 0 V  
4. Tch ≤ 125°C, VDD = 100 V, RG = 25 Ω  
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When  
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated  
voltage may be applied to this device.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No.  
Date Published May 2002 NS CP(K)  
Printed in Japan  
G15937EJ1V0DS00 (1st edition)  
2001  
©
12345678

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