Datasheet > TNETA1585PGF

TNETA1585PGF

更新时间： 2024-09-17 02:58:43

品牌	Logo	应用领域
德州仪器 - TI		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
32页	464K
描述
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES

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TNETA1585PGF 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP, QFP176,1.0SQ,20	针数：	176
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
Factory Lead Time：	1 week	风险等级：	5.88
应用程序：	ATM	JESD-30 代码：	S-PQFP-G176
长度：	24 mm	功能数量：	1
端子数量：	176	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP176,1.0SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3,5 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
子类别：	ATM/SONET/SDH ICs	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	24 mm
Base Number Matches：	1

TNETA1585PGF 数据手册

TNETA1585

ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE

WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES

SDNS041A – NOVEMBER 1996 – REVISED JULY 1998

Single-Chip Scheduler for Scheduling

Available Bit Rate (ABR) Connections

Supports TM4.0-Defined Resource

Management (RM)-Cell Formats and

Provides the RM-Cell Payload and

Information on How to Configure the

RM-Cell Header to the Segmentation and

Reassembly (SAR) Device

Used With the TNETA1575 to Provide a

Complete Solution for Segmentation and

Reassembly of Data on ABR Connections

as Specified in the Asynchronous Transfer

Mode (ATM) Forum’s Traffic Management

4.0 Document (TM4.0) and ITU-TI.371

Supports Out-of-Rate Forward and

Backward RM-Cell Generation to Prevent

Deadlock Situations When the Rates of

Sources and Destinations Are Driven to or

Below a Minimum Cell Rate of 10 Cells Per

Second

Supports Scheduling of Variable-Bit-Rate

Non-Real Time (VBR-nrt) Using

Host-Programmable Peak Cell Rate (PCR),

Sustained Cell Rate (SCR), and Maximum

Burst Size (MBS)

Processes Received RM Cells, Maintaining

Parameters and Variables in Accordance

With TM4.0

On-Chip Self-Sorting FIFO-Based

Scheduler Used to Schedule the

Transmission of Cells for All Connections

Hardware Assistance Is Provided for 1/ACR

Calculations That Support Scheduling

Operations to Maximize Performance

Simultaneously Supports Both Virtual Path

(VP) and Virtual Channel (VC) Level ABR

Traffic Management

Hardware Assistance Is Provided for 15-Bit

Floating-Point To/From Integer

Conversions to Maximize Performance

Provides Scheduling for up to 2047 ABR

Connections Required for Large-Scale LAN

Emulation Installations

UTOPIA Level-1 Revision-2.01 Receive

(Observe-Only) Cell Interface

On-Chip Processors Implement the

End-System Behavior as Defined in TM4.0,

Providing a High-Performance and Flexible

Solution to Track Future Standards

Internal 8-Cell Receive FIFO

Receive-Cell Interface Can Be Programmed

to Operate as Either a Physical (PHY-Layer)

Interface or as a SAR/Switch (ATM-Layer)

Interface.

On-Chip Instruction RAMs Hold the

Microcode for the Source and Destination

Processors, Providing Fast Execution of

Code on Chip

Supports Boundary Scan Through a

Five-Wire JTAG Interface in Accordance

With IEEE Std 1149.1-1990 (Includes IEEE

Std 1149.1a-1993) IEEE Standard Test-

Access-Port and Boundary-Scan

Architecture

Configuration Support for All Primary and

Optional TM4.0 Parameters, Providing

Maximum Implementation Flexibility

description

The TNETA1585 is an asynchronous transfer mode (ATM) programmable traffic management scheduler device

that is used with a segmentation and reassembly (SAR) device to provide a flexible, high-performance solution

for the available bit rate (ABR) service category. Its programmability enables it to support other special modes

including variable-bit-rate non-real-time (VBR-nrt) service category and virtual-path (VP)-level ABR in addition

to and simultaneously with ABR. Combining the TNETA1585 with the TNETA1575 provides a high-performance

solution for classical LAN-to-ATM backbone applications, including high-performance networking hubs.

This data sheet provides information on the device hardware specifications that includes device interfaces,

timing diagrams, electrical characteristics, terminal and package information, and an overview of device

operation. All information on the TNETA1585 data structures, configuration, and features is provided in the

TNETA1585 Programmer’s Reference Guide, literature number SDNU016.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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