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TNETE110APCM

更新时间： 2024-11-24 02:58:39
品牌 Logo 应用领域
德州仪器 - TI 局域网（LAN）标准以太网：16GBASE-TPC
页数 文件大小 规格书
24页 357K
描述
PCI ETHERNETE CONTROLLER SINGLE-CHIP 10 BASE-T

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TNETE110APCM 数据手册

 浏览型号TNETE110APCM的Datasheet PDF文件第2页浏览型号TNETE110APCM的Datasheet PDF文件第3页浏览型号TNETE110APCM的Datasheet PDF文件第4页浏览型号TNETE110APCM的Datasheet PDF文件第5页浏览型号TNETE110APCM的Datasheet PDF文件第6页浏览型号TNETE110APCM的Datasheet PDF文件第7页 
ThunderLAN TNETE110A  
PCI ETHERNET CONTROLLER  
SINGLE-CHIP 10 BASE-T  
SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996  
Single-Chip Ethernet Adapter for the  
Peripheral Component Interconnect (PCI)  
Local Bus  
Integrated 10 Base-T, and 10 Base-5  
Attachment Unit Interface (AUI) Physical  
Layer Interface  
– Single-Chip IEEE 802.3 and Blue Book  
Ethernet-Compliant Solution  
– DSP-Based Digital Phase-Locked Loop  
– Smart Squelch Allows for Transparent  
Link Testing  
†
– 32-Bit PCI Glueless Host Interface  
– Compliant With PCI Local-Bus  
Specification (Revision 2.0)  
– 33-MHz Operation  
– 3-V or 5-V I/O Operation  
– Adaptive Performance Optimization  
(APO) by Texas Instruments (TI ) for  
Highest Available PCI Bandwidth  
– High-Performance Bus Master  
Architecture With Byte-Aligning DMA  
Controller for Low Host CPU and Bus  
Utilization  
– Transmission Waveshaping  
– Autopolarity (Reverse Polarity  
Correction)  
– External/Internal Loopback Including  
Twisted Pair and AUI  
– 10 Base-2 Supported Via AUI Interface  
Low-Power CMOS Technology  
– Green PC Compatible  
– Microsoft Advanced Power  
Management  
– Plug-and-Play Compatible  
Supports 32-Bit Data Streaming on PCI Bus  
– Time Division Multiplexed SRAM  
– 2-Gbps Internal Bandwidth  
EEPROM Interface Supports Jumperless  
Design and Autoconfiguration  
Driver Compatible With All Previous  
ThunderLAN Components  
Hardware Statistics Registers for  
Switched-Ethernet Compatible  
Management Information Base (MIB)  
Full-Duplex Compatible With Independent  
Transmit and Receive Channels  
DMTF (Desktop Management Task Force)  
Compatible  
‡
No On-Board Memory Required  
IEEE Standard 1149.1 Test Access Port  
(JTAG)  
Auto-Negotiation (N-Way) Compatible  
144-Pin Quad Flat Packages (PCM Suffix)  
and Thin Quad Flat Packages (PGE Suffix)  
Supports the Card Bus CIS Pointer  
Register  
10 Base-T  
Ethernet  
10 Base-T  
Physical  
Layer  
FIFO  
Registers  
Ethernet  
LAN  
Controller  
10 Mbps  
PCI  
Bus Master  
Control  
Interface  
10 Base-5  
(AUI)  
PCI  
Bus  
Multiplexed  
SRAM  
FIFO  
Figure 1. ThunderLAN Architecture  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
‡
The PCI Local-Bus Specification, Revision 2.0 should be used as a reference with this document.  
IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture  
ThunderLAN, Adaptive Performance Optimization, and TI are trademarks of Texas Instruments Incorporated.  
Ethernet is a trademark of Xerox Corporation.  
Microsoft is a trademark of Microsoft Corporation.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
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