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TNETE2101APZ PDF预览

TNETE2101APZ

更新时间： 2024-11-26 03:27:03
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
39页 497K
描述
10BASE-T/100BASE-TX/100BASE-FX LOW-POWER PHYSICAL-LAYER INTERFACE

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中文翻译

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TNETE2101APZ 技术参数

是否无铅： 含铅生命周期：Obsolete
零件包装代码：QFP包装说明：LFQFP,
针数：100Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.79
JESD-30 代码：S-PQFP-G100长度：14 mm
功能数量：1端子数量：100
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
认证状态：Not Qualified座面最大高度：1.6 mm
标称供电电压：3.3 V表面贴装：YES
技术：CMOS电信集成电路类型：ETHERNET TRANSCEIVER
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

TNETE2101APZ 数据手册

 浏览型号TNETE2101APZ的Datasheet PDF文件第2页浏览型号TNETE2101APZ的Datasheet PDF文件第3页浏览型号TNETE2101APZ的Datasheet PDF文件第4页浏览型号TNETE2101APZ的Datasheet PDF文件第5页浏览型号TNETE2101APZ的Datasheet PDF文件第6页浏览型号TNETE2101APZ的Datasheet PDF文件第7页 
TNETE2101  
10BASE-T/100BASE-TX/100BASE-FX  
LOW-POWER PHYSICAL-LAYER INTERFACE  
SPWS032D – JANUARY 1997 – REVISED MARCH 1999  
Integrated, Single-Chip, Ethernet  
Physical-Layer (PHY) Interface for  
Full-Duplex or Half-Duplex Connection to  
10BASE-T, 100BASE-TX, and 100BASE-FX  
Networks  
10BASE-T  
– Fully Compliant With IEEE Std 802.3  
– Smart Squelch for Improved Noise  
Immunity  
– Integrated Transmit Wave Shaping  
– Autopolarity (Reverse-Polarity  
Correction)  
Low-Power 3.3-V CMOS Design With  
Power-Down Capability for CardBus and  
Other Applications Requiring Low Power  
– Transmit Jabber Detection  
100BASE-TX  
Integrated Transmit Filtering and Receive  
Equalization Provide for Minimal External  
Component Count to Reduce System Cost  
– Fully Compliant With ANSI Twisted-Pair  
Physical-Media-Dependent (TP-PMD)  
Standard and IEEE Std 802.3  
– Synthesized Rise-Time Control  
– Integrated Receiver With Adaptive Line  
Equalization (EQ) and Baseline Wander  
(BLW) Correction (DC Restoration)  
10BASE-T/100BASE-TX Connection  
Supported With Magnetics Package and  
RJ-45 Connector  
Electrostatic Discharge (ESD) Human Body  
Model (HBM) Protection 1.5 kV Per JEDEC  
JESD 22-A114-A  
IEEE Std 802.3-Compliant  
Media-Independent Interface (MII) That  
Includes Management Interface  
Digital Signal Processor (DSP)-Based  
Digital Phase-Locked Loop (PLL)  
Technology Allows Data Recovery at  
10 Mbit/s and 100 Mbit/s, Requiring One  
20-MHz Clock Reference Source  
IEEE Std 802.3-Compliant Autonegotiation  
(N-Way) With Next-Page Support  
IEEE Std 1149.1 (JTAG) Test Access Port  
(TAP)  
Packaged in 100-Terminal Plastic Quad  
Flatpack  
100BASE-TX  
Physical Coding Sublayer  
(PCS) and  
Physical Medium Attachment  
(PMA)  
MII Data  
and  
Control  
Interface  
10/100 PMD  
– BLW Correct  
– Adaptive EQ  
– MLT-3  
Magnetics  
RJ-45  
10BASE-T  
10/100 MAC  
MII  
PCS and PMA  
MII  
PLL Clock  
Generation  
and Recovery  
Autonegotiation  
With Next-Page  
Support  
Management  
Registers  
JTAG  
Figure 1. 10BASE-T/100BASE-TX PHY  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TI is a trademark of Texas Instruments Incorporated.  
Ethernet is a registered trademark of Xerox Corporation.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...39

中文翻译

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TNETE2101APZ 替代型号

型号 品牌 替代类型 描述 数据表
TNETE2101PZ TI

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