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TNETE2004PBE

更新时间： 2024-11-22 22:19:27
品牌 Logo 应用领域
德州仪器 - TI 网络接口电信集成电路电信电路以太网：16GBASE-T
页数 文件大小 规格书
46页 721K
描述
MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

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TNETE2004PBE 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：HQFP, QFP120,1.2SQ,32针数：120
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.84Is Samacsys：N
JESD-30 代码：S-PQFP-G120长度：28 mm
功能数量：1端子数量：120
收发器数量：4最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：HQFP封装等效代码：QFP120,1.2SQ,32
封装形状：SQUARE封装形式：FLATPACK, HEAT SINK/SLUG
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：4.1 mm
子类别：Network Interfaces最大压摆率：0.0001 mA
标称供电电压：5 V表面贴装：YES
技术：CMOS电信集成电路类型：ETHERNET TRANSCEIVER
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：28 mm
Base Number Matches：1

TNETE2004PBE 数据手册

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TNETE2004  
MDIO-MANAGED QuadPHY  
FOUR 10BASE-T PHYSICAL-LAYER INTERFACES  
SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997  
Single-Chip Multi-PHY Solution:  
– Four 10BASE-T Physical-Layer (PHY)  
Interfaces in One Package Minimizing  
PCB Footprint for Internetworking  
Applications  
Loopback Mode for Test Operations  
Integrated Manchester Encoding/Decoding  
Receive-Clock Regeneration for All Input  
Channels  
Smart Squelch  
Each PHY is Half-Duplex and Full-Duplex  
Compliant  
– Full-Duplex: Independent Transmit and  
Receive Channels for Operation at  
20-Mbit/s Aggregate  
Transmit Pulse Shaping  
Collision Detection  
Jabber Detection  
Link-Pulse Detection  
Auto-Polarity Control  
Compliant With IEEE Std 802.3 10BASE-T  
Specification  
Simple Connection for LED Status  
Indicators  
Management Data Input/Output (MDIO)  
Serial Compliant With IEEE Std 802.3  
Media-Independent Interface (MII)  
Sufficient Current Drive to Directly Connect  
LED Status Indicators  
Integrated Filters on Both Receive and  
Transmit Circuits  
– No External Filters Are Required  
– Meets IEEE Std 802.3 (Section 14.3)  
Electrical Requirements  
CMOS Technology Enables Low Power  
Consumption  
Power-Down Mode  
†
IEEE Std 1149.1 (JTAG) Test-Access Port  
(TAP)  
Implements IEEE Std 802.3u  
Auto-Negotiation to Establish the Highest  
Common Protocol  
Each Serial Network Interface (SNI) Signal  
Is User Programmable  
DSP-Based Digital Phase-Locked Loop  
(PLL)  
Package Options Include 120-Pin Plastic  
Quad Flat Package (PBE) and 128-Pin  
Plastic Quad Flat Package (PAC)  
Interrupt Feature on MDIO  
description  
The TNETE2004 QuadPHY interface device is a single-chip, multi-PHY (four 10BASE-T devices),  
high-performance solution for designers of 10BASE-T networking systems. The highly integrated TNETE2004  
includesauser-programmableSNIsignalforeachPHY. EachPHYinterfaceonthedeviceprovidesManchester  
encoding/decoding of data via unshielded twisted-pair (UTP) balanced cable through simple isolation  
transformers requiring no external filtering. Additional TNETE2004 features are smart squelch, jabber  
detection, auto-polarity correction, transmission wave shaping, and anti-alias filtering capabilities. Each PHY  
interface on the TNETE2004 is individually addressable within the TNETE2004 via the MDIO.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
IEEE Std 1149.1-1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...46

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