TNETE2008
OctalPHY
EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES
SPWS042B – DECEMBER 1997 – REVISED JUNE 1998
Single-Chip With Eight Physical-Layer
(PHY) Interfaces for Internetworking
Applications
Intelligent Squelch With Selectable
Threshold
Link-Pulse Detection and Autonegotiation
Intelligent Rejection of MLT-3 Encoded Data
Each PHY Is Full-Duplex Capable for
Simultaneous Transmit and Receive
Transmit Pulse Shaping Reduces
Electromagnetic Interference (EMI)
Compliant With IEEE Std 802.3 10BASE-T
Specification
Clock Synchronization Between Channels
Collision Detection
Integrated Filters on Both Receive and
Transmit Circuits
– No External Filters Are Required
– Meets IEEE Std 802.3 (Section 14.3)
Electrical Requirements
Built-In Jabber Detection
Automatic Reversed-Polarity Detection and
Correction
Implements IEEE Std 802.3 Autonegotiation
to Establish the Highest Common Protocol
Sufficient Current Drive to Directly Connect
LED Status Indicators
Electrostatic Discharge (ESD) Human Body
Model (HBM) Protection 1.5 kV Per JEDEC
JESD22-A114A
CMOS Technology Enables Low Power
Consumption
3.3-V Operation
Digital Signal Processor (DSP)-Based
Digital Phase-Locked Loop (PLL)
†
IEEE Std 1149.1 (JTAG) Test-Access Port
(TAP)
Loopback Mode for Test Operations
Direct Drive to Network Coupling
Magnetics
Integrated Manchester Encoding/Decoding
Receive-Clock Regeneration for All Input
Channels Using Digital PLL
Packaged in 120-Pin Plastic Quad Flatpack
(PQFP)
FIFOs Accommodate 8x IEEE Limit on
Per-Channel-Pair Frequency Mismatch
Across All Eight Channels (IEEE Std 802.3,
Sec 7.3.2)
description
The TNETE2008 OctalPHY is a physical-layer (PHY) interface device for up to eight 10BASE-T networks using
a multiplexed medium access controller (MAC) interface compatible with TNETX3110, TNETX3151,
TNETX3190, or TNETX3270 switch devices, or equivalent. A digital-signal-processor (DSP)-based
phase-locked loop (PLL) is used on each channel to recover data. Integrated wave shaping of the output
eliminates the need for filters to meet electromagnetic interference (EMI) testing. DSP-based wave-shaping
techniques used internally reduce the required number of external components to a coupling transformer, four
resistors, and a capacitor per channel. The multiplexed host interface reduces the number of terminals required
to connect eight networks to eight MAC engines, allowing the use of a single package.
The TNETE2008 operation is fully automatic. It can be taken from reset to full operation without parameter
downloads or interaction with a host central processing unit (CPU). Some mode terminals affect all of the ports,
such as looping back transmit data to the receive path, powering down the PHY, and setting the receiver
threshold. There are no management interfaces or internal registers on this device. A directly driven LED matrix
provides Ethernet status indicators, i.e., link, activity, collision, and duplex. The TNETE2008 produces and
receives IEEE Std 802.3-compliant waveforms when coupled to the network with a suitable transformer. The
TNETE2008 also incorporates a JTAG-compliant test port.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
IEEE Std 1149.1-1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture
Ethernet is a trademark of Xerox Corporation.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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