ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
Single-Chip Ethernet Controller for the
Integrated 10 Base-T, and 10 Base-5
Arithmetic Unit Interface (AUI)
Physical-Layer Interface
– Single-Chip IEEE 802.3 and Blue Book
Ethernet-Compliant Solution
– DSP-Based Digital Phase-Locked Loop
– Smart Squelch Allows for Transparent
Link Testing
Peripheral Component Interconnect (PCI)
Local Bus
†
– 32-Bit PCI Glueless Host Interface
– Compliant With PCI Local-Bus
Specification (Revision 2.0)
– 0-MHz to 33-MHz Operation
– 3-V or 5-V I/O Operation
– Adaptive Performance Optimization
(APO) by Texas Instruments (TI ) for
Highest Available PCI Bandwidth
– High-Performance Bus Master
Architecture With Byte-Aligning Direct
Memory Access (DMA) Controller for
Low Host CPU and Bus Utilization
– Plug-and-Play Compatible
– Transmission Waveshaping
– Autopolarity (Reverse Polarity
Correction)
– External/Internal Loopback Including
Twisted Pair and AUI
– 10 Base-2 Supported Through AUI
Interface
Media-Independent Interface (MII) for
Connecting 100-Mbps External
Transceivers
– Compliant MII for IEEE 802.3u
Transceivers
Supports 32-Bit Data Streaming on PCI Bus
– Time-Division Multiplexed Static
Random-Access Memory (SRAM)
– 2-Gbps Internal Bandwidth
– Supports 100 Base-TX, 100 Base-T4, and
100 Base-FX
– Super Set Supports IEEE 802.12
Transceivers
– Supports Ethernet and Token-Ring
Framing Formats for 100VG-AnyLAN
– Link-Pulse Detection for Determining
Wire Rate
Driver Compatible With All Previous
ThunderLAN Components
Switched Ethernet Compatible
Full-Duplex Compatible
– Independent Transmit and Receive
Channels
– Two Transmit Channels for Demand
Priority
Low-Power CMOS Technology
– Green PC Compatible
– Microsoft Advanced Power
Management
Supports Multiple Protocols With a Single
Driver Suite–Optimized Shared Interrupts
No On-Board Memory Required
Auto-Negotiation (N-Way) Compatible
Multimedia-Ready Architecture
EEPROM Interface Supports Jumperless
Design and Autoconfiguration
Hardware Statistics Registers for
Management-Information Base (MIB)
Supports the Card-Bus Card Information
Structure (CIS) Pointer Register
DMTF (Desktop Management Task Force)
Compatible
‡
IEEE Standard 1149.1 Test-Access Port
(JTAG)
144-Pin Quad Flat Packages (PCM Suffix)
and Thin Quad Flat Packages (PGE Suffix)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
‡
The PCI Local-Bus Specification, Revision 2.0 should be used as a reference with this document.
IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture
ThunderLAN, Adaptive Performance Optimization, and TI are trademarks of Texas Instruments Incorporated.
Ethernet is a registered trademark of Xerox Corporation.
Microsoft is a registered trademark of Microsoft Corp.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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