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TN5325N3 PDF预览

TN5325N3

更新时间： 2024-09-19 22:19:27
品牌 Logo 应用领域
超科 - SUPERTEX /
页数 文件大小 规格书
2页 448K
描述
N-Channel Enhancement-Mode Vertical DMOS FETs

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中文翻译

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TN5325N3 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TO-92包装说明：CYLINDRICAL, O-PBCY-W3
针数：3Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8541.21.00.95
风险等级：5.29其他特性：HIGH INPUT IMPEDANCE
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：250 V
最大漏极电流 (ID)：0.215 A最大漏源导通电阻：7 Ω
FET 技术：METAL-OXIDE SEMICONDUCTOR最大反馈电容 (Crss)：23 pF
JEDEC-95代码：TO-92JESD-30 代码：O-PBCY-W3
JESD-609代码：e0元件数量：1
端子数量：3工作模式：ENHANCEMENT MODE
最高工作温度：150 °C封装主体材料：PLASTIC/EPOXY
封装形状：ROUND封装形式：CYLINDRICAL
峰值回流温度（摄氏度）：NOT SPECIFIED极性/信道类型：N-CHANNEL
最大功率耗散 (Abs)：0.74 W认证状态：Not Qualified
子类别：FET General Purpose Power表面贴装：NO
端子面层：Tin/Lead (Sn/Pb)端子形式：WIRE
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

TN5325N3 数据手册

 浏览型号TN5325N3的Datasheet PDF文件第2页 
TN5325  
Low Threshold  
N-Channel Enhancement-Mode  
Vertical DMOS FETs  
Ordering Information  
Product marking for SOT-23:  
N3C❋  
Order Number / Package  
BVDSS  
/
RDS(ON)  
VGS(th)  
ID(on)  
BVDGS  
(max)  
(max)  
(min)  
TO-236AB*  
TO-92  
TO-243AA**  
where ❋ = 2-week alpha date code  
250V  
7.0Ω  
2.0V  
1.2A  
TN5325K1  
TN5325N3  
TN5325N8  
*
Same as SOT-23. All units shipped on 3,000 piece carrier tape reels.  
** Shipped on 2,000 piece carrier tape and reels.  
Product marking for TO-243AA  
Features  
TN3C❋  
Where❋=2-weekalphadatecode  
❏
❏
❏
❏
❏
❏
❏
Low threshold – 2.0V max.  
Free from secondary breakdown  
Low power drive requirement  
Low CISS and fast switching speeds  
Excellent thermal stability  
Advanced DMOS Technology  
These enhancement-mode (normally-off) transistors utilize a  
vertical DMOS structure and Supertex’s well-proven silicon-gate  
manufacturing process. This combination produces devices with  
the power handling capabilities of bipolar transistors and with the  
high input impedance and positive temperature coefficient inher-  
ent in MOS devices. Characteristic of all MOS structures, these  
devices are free from thermal runaway and thermally-induced  
secondary breakdown.  
High input impedance and high gain  
Complementary N- and P-channel devices  
Applications  
❏
❏
❏
❏
❏
❏
❏
Logic level interfaces – ideal for TTL and CMOS  
Supertex’s vertical DMOS FETs are ideally suited to a wide range  
of switching and amplifying applications where high breakdown  
voltage, high input impedance, low input capacitance, and fast  
switching speeds are desired.  
Solid state relays  
Battery operated systems  
Photo voltaic drives  
Analog switches  
General purpose line drivers  
Telecom switches  
Package Options  
Absolute Maximum Ratings  
Drain-to-Source Voltage  
D
G
BVDSS  
D
G
D
S
Drain-to-Gate Voltage  
BVDGS  
S
S G  
D
Gate-to-Source Voltage  
± 20V  
TO-243AA  
(SOT-89)  
TO-236AB  
(SOT-23)  
TO-92  
Operating and Storage Temperature  
Soldering Temperature*  
-55°C to +150°C  
300°C  
Note: See Package Outline section for dimensions.  
* Distance of 1.6 mm from case for 10 seconds.  
11/12/01  
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability  
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to  
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the  
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.  
12

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