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TN5325N8GP002 PDF预览

TN5325N8GP002

更新时间: 2024-11-11 02:52:11
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美国微芯 - MICROCHIP /
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14页 596K
描述
N-Channel Enhancement-Mode Vertical DMOS FET

TN5325N8GP002 数据手册

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TN5325  
N-Channel Enhancement-Mode Vertical DMOS FET  
Features  
General Description  
• Low Threshold (2V Maximum)  
The TN5325 is a low-threshold, Enhancement-mode  
(normally-off) transistor that utilizes a vertical DMOS  
structure and a well-proven silicon gate manufacturing  
process. This combination produces a device with the  
power handling capabilities of bipolar transistors and  
the high input impedance and positive temperature  
coefficient inherent in MOS devices. Characteristic of  
all MOS structures, this device is free from thermal  
runaway and thermally induced secondary breakdown.  
• High Input Impedance and High Gain  
• Free from Secondary Breakdown  
• Low CISS and Fast Switching Speeds  
Applications  
• Logic-level Interfaces (Ideal for TTL and CMOS)  
• Solid State Relays  
Microchip’s vertical DMOS FETs are ideally suited to a  
wide range of switching and amplifying applications  
where very low threshold voltage, high breakdown  
voltage, high input impedance, low input capacitance  
and fast switching speeds are desired.  
• Battery-operated Systems  
• Photo-voltaic Drives  
• Analog Switches  
• General Purpose Line Drivers  
Telecommunication Switches  
Package Types  
3-lead SOT-23 (TO-236AB)  
3-lead TO-92  
(Top view)  
3-lead SOT-89 (243AA)  
(Top view)  
(Top view)  
DRAIN  
DRAIN  
SOURCE  
DRAIN  
GATE  
SOURCE  
DRAIN  
GATE  
SOURCE  
GATE  
See Table 2-1, Table 2-2 and Table 2-3 for pin information.  
2017 Microchip Technology Inc.  
DS20005709A-page 1  

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