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TC358764XBG PDF预览

TC358764XBG

更新时间： 2024-11-10 14:56:55
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
26页 493K
描述
EOL announced

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中文翻译

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TC358764XBG 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：TFBGA-49Reach Compliance Code：unknown
风险等级：5.76JESD-30 代码：S-PBGA-B49
长度：5 mm端子数量：49
最高工作温度：85 °C最低工作温度：-30 °C
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装形状：SQUARE封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
座面最大高度：1.2 mm最大供电电压：1.3 V
最小供电电压：1.1 V标称供电电压：1.2 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子形式：BALL
端子节距：0.65 mm端子位置：BOTTOM
宽度：5 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUIT
Base Number Matches：1

TC358764XBG 数据手册

 浏览型号TC358764XBG的Datasheet PDF文件第2页浏览型号TC358764XBG的Datasheet PDF文件第3页浏览型号TC358764XBG的Datasheet PDF文件第4页浏览型号TC358764XBG的Datasheet PDF文件第5页浏览型号TC358764XBG的Datasheet PDF文件第6页浏览型号TC358764XBG的Datasheet PDF文件第7页 
TC358764XBG/TC358765XBG  
CMOS Digital Integrated Circuit Silicon Monolithic  
TC358764XBG/TC358765XBG  
Mobile Peripheral Devices  
TC358764XBG  
Overview  
The primary function of TC358764XBG/TC358765XBG is DSI-to-LVDS  
Bridge, enabling video streaming output over DSI link to drive  
LVDS-compatible display panels. The chip supports up to 1366×768  
24-bit pixel resolution for single-link LVDS and up to WUXGA (1920x1200  
P-TFBGA49-0505-0.65AZ  
18-bit pixels) resolution for dual-link LVDS. As a secondary function, the  
chip also supports an I2C Master which is controlled by the DSI link; this  
may be used as an interface to any other control functions through I2C.  
The chip can be configured through the DSI link by sending write register  
commands through DSI Generic Long Write-packets. It can also be  
configured through the I2C Slave interface.  
Weight: 53 mg (Typ.)  
TC358765XBG  
P-TFBGA64-0606-0.65AZ  
Weight: 75 mg (Typ.)  
Features  
● DSI Receiver  
● System Operation  
Configurable 1- up to 4-Data-Lane DSI Link with  
bi-directional support on Data Lane 0  
Maximum bit rate of 800 Mbps/lane  
Video input data formats:  
Host configures the chip through DSI link  
Through DSI link, Host accesses the chip register set  
using Generic Write and Read packets. One Generic  
Long Write packet can write to multiple contiguous  
register addresses  
- RGB565 16 bits per pixel  
- RGB666 18 bits per pixel  
- RGB666 loosely packed 24 bits per pixel  
- RGB888 24 bits per pixel.  
Includes an I2C Master function which is controlled  
by Host through DSI link (multi-master is not  
supported)  
Video frame size:  
Power management features to save power  
Configuration registers is also accessible through  
I2C Slave interface  
- Up to 1366×768 24-bit/pixel resolution to  
single-link LVDS display panel  
- Up to WUXGA resolutions (1920×1200 18-bit  
pixels) to dual-link LVDS display panel  
Supports Video Stream packets for video data  
transmission.  
● Clock Source  
LVDS pixel clock source is either from external  
clock EXTCLK or derived from DSICLK.  
A built-in PLL generates the high-speed LVDS  
serializing clock requiring no external components  
Supports generic long packets for accessing the  
chip’s register set  
Supports the path for Host to control the on-chip I2C  
Master  
● Digital Input/Output Signals  
All Digital Input signals are 3.3V tolerant  
All Digital Output signals can output ranging from  
1.8V to 3.3V depending on IO supply voltage  
● LVDS FPD Link Transmitter  
Supports single-link or dual-link  
Maximum pixel clock frequency of 85 MHz  
Maximum throughput of 297.5 MBytes/sec for  
single-link or 595 Mbytes/sec for dual-link  
Supports display up to 1366×768 24-bit/pixel  
resolution for single-link, or up to WUXGA (18  
bit/pixel) resolutions for dual-link  
Supports the following pixel formats:  
- RGB666 18 bits per pixel  
- RGB888 24 bits per pixel  
Flexible mapping of parallel data input bit ordering  
Supports power-down  
● Power supply  
MIPI® DSI D-PHY: 1.2 V  
LVDS PHY: 3.3 V  
I/O:  
be same level)  
Digital Core: 1.2 V  
1.8 V - 3.3V (all IO supply pins must  
● Power Consumption  
Power –down mode is achieved by:  
1. Disable PLL (0x04A0[8] = 1) and LVDS  
(0x049C[0] = 0) after stopping video stream (in  
DSI LP11 state)  
2. Drive DSI Data Lanes to LP00 state  
3. Stop DSIClk and/or RefClk  
© 2014-2018  
Toshiba Electronic Devices & Storage Corporation  
1 / 26  
2018-04-04  
Rev. 1.33  
1234567...26

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