TC358771XBG/TC358772XBG
CMOS Digital Integrated Circuit Silicon Monolithic
TC358771XBG/TC358772XBG
Mobile Peripheral Devices
TC358771XBG
Overview
The TC358771XBG/TC358772XBG Functional Specification adds
back light engine to function of TC358775XBG.
TC358771XBG/TC358772XBG is the follow-up chip of
TC358774XBG/TC358775XBG, which:
P-VFBGA49-0505-0.65-001
Weight: 31 mg (Typ.)
1. Is pin compatible to TC358774XBG/TC358775XBG
2. Exhibit LVDS Tx block operates at 1.8V @135 MHz to reduce operation power
3. Back light engine controls the back light level automatically with
TC358772XBG
ambient light and adjusts image contents.
The primary function of this chip is DSI-to-LVDS Bridge, enabling
video streaming output over DSI link to drive LVDS-compatible display
panels. The chip supports up to 1600x1200 24-bit pixel resolution for
single-link LVDS and up to WUXGA (1920x1200 24-bit pixels)
resolution for dual-link LVDS. As a secondary function, the chip also
supports an I2C Master which is controlled by the DSI link; this may be
used as an interface to any other control functions through I2C.
P-VFBGA64-0606-0.65-001
Weight: 47mg (Typ.)
Features
● DSI Receiver
Supports the following pixel formats:
Configurable 1- up to 4-Data-Lane DSI Link with
bi-directional support on Data Lane 0
- RGB666 18 bits per pixel
- RGB888 24 bits per pixel
Features Toshiba Magic Square algorithm which
enables a RGB666 display panel to produce a
display quality almost equivalent to that of an
RGB888 24-bit panel
Maximum bit rate of 1 Gbps/lane
Video input data formats:
- RGB565 16 bits per pixel
- RGB666 18 bits per pixel
- RGB666 loosely packed 24 bits per pixel
- RGB888 24 bits per pixel
Video frame size:
Flexible mapping of parallel data input bit ordering
Supports programmable clock polarity
Supports two power saving states
- Sleep state, when receiving DSI ULPS signaling
- Standby state, entered by STBY pin assertion
- Up to 1600×1200 24-bit/pixel resolution to
single-link LVDS display panel, limited by 135 MHz
LVDS speed
- Up to WUXGA resolutions (1920×1200 24-bit
pixels) to dual-link LVDS display panel, limited by
4 Gbps DSI link speed
● Back Light Engine
Provides a proper backlight parameter to the
environment light
Supports Video Stream packets for video data
● System Operation
Host configures the chip through DSI link
Through DSI link, Host accesses the chip register
set using Generic Write and Read packets. One
Generic Long Write packet can write to multiple
contiguous register addresses
transmission.
Supports generic long packets for accessing the
chip's register set
Supports the path for Host to control the on-chip
I2C Master
Includes an I2C Master function which is controlled
by Host through DSI link (multi-master is not
supported)
● LVDS FPD Link Transmitter
Supports single-link or dual-link
Maximum pixel clock frequency of 135 MHz.
Power management features to save power
Supports display up to 1600×1200 24-bit/pixel
resolution for single-link, or up to 1920×1200
24-bit resolutions for dual-link
Configuration registers is also accessible through
I2C Slave interface
© 2014-2017
Toshiba Electronic Devices & Storage Corporation
1 / 21
2017-10-31
Rev. 1.0
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