Datasheet > TC358840XBG

TC358840XBG

更新时间： 2024-10-03 14:58:11

品牌	Logo	应用领域
东芝 - TOSHIBA		电视
页数	文件大小	规格书
21页	446K
描述
digital media adapter (DMA) / smart monitor / smart set-top box / smart TV

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技术参数
数据手册

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TC358840XBG 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	VFBGA,	Reach Compliance Code：	unknown
风险等级：	5.8	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-PBGA-B80	长度：	7 mm
功能数量：	1	端子数量：	80
最高工作温度：	70 °C	最低工作温度：	-30 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	VFBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	座面最大高度：	1 mm
最大供电电压 (Vsup)：	1.2 V	最小供电电压 (Vsup)：	1.1 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子形式：	BALL
端子节距：	0.65 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7 mm
Base Number Matches：	1

TC358840XBG 数据手册

TC358840XBG

CMOS Digital Integrated Circuit Silicon Monolithic

TC358840XBG

Mobile Peripheral Devices

TC358840XBG

Overview

TC358840XBG, Ultra HD to CSI-2, bridge converts high resolution

(higher than 4 Gbps) HDMI® stream to MIPI® CSI-2 Tx video. It is a

follow up device of TC358743XBG. The HDMI-RX runs at 297 MHz to

carry up to 7.2 Gbps video stream. It requires dual link MIPI CSI-2 Tx,

1 Gbps/data lane, to transmit out a maximum 7.2 Gbps video data.

P-VFBGA80-0707-0.65-001

Weight: 67 mg (Typ.)

The bridge chip is necessary for current and next generation

Application Processors which have been designed without video

stream input port except CSI-2 Rx.

Features

● HDMI-RX Interface

video stream and CSI1 carries the right one at

the default configuration.

- Left or right data can be

assigned/programmed to either CSI-2 Tx link

- The maximum length of each half is limited to

2048-pixel, CSI0 data length could be

different from that of CSI1's

 HDMI 1.4b

- Video Formats Support (Up to 4K×2K / 30fps),

maximum 24 bps (bit-per-pixel) no deep color

support

 RGB, YCbCr444: 24-bpp

 YCbCr422: 24-bpp

- The maximum Hsync skew between CSI0

and CSI1 can be less than 10 ByteClk

 Single link CSI-2, maximum horizontal pixel

width

- 2558 pixels (24-bit per pixel)

- 3411 pixels (16-bit per pixel)

 HDMI InfoFrame data can be transmit over MIPI

CSI-2 at the beginning of each frame (after FS

short packet)

- Color Conversion

 4:2:2 to 4:4:4 is supported

 4:4:4: to 4:2:2 is supported

 RGB888 to YCbCr (4:4:4 / 4:2:2) is

supported

 YCbCr (4:4:4 / 4:2:2) to RGB888/666 is

supported

 Note: for RGB666 (R=R[5:0],2'b00,

G=G[5:0],2'b00, B=G[5:0],2'b00)

- Maximum HDMI clock speed: 297 MHz

- Audio Supports

 Internal Audio PLL to track N/CTS value

transmitted by the ACR packet.

- 3D Support

 Supports video data formats

- RGB666, RGB888, YCbCr444, YCbCr 422

24-bit and YCbCr 422 16-bit

- YCbCr inputs can be converted into RGB

before outputting and vice versa.

- Support HDCP1.4 decryptions (optional)

- EDID Support, Release A, Revision 1 (Feb 9,

2000)

 First 128 byte (EDID 1.3 structure)

 First E-EDID Extension: 128 bytes of CEA

Extension version 3 (specified in

CEA-861-D)

● I²C Interface

 Support for normal (100 kHz), fast mode (400

kHz) and ultrafast mode (2 MHz)

 Slave Mode

- To be used by an external Master to configure

all TC358840XBG internal registers, including

EDID_SRAM and panel control

 Embedded 1K-byte SRAM (EDID_SRAM)

 Does not support Audio Return Path and HDMI

Ethernet Channels

- Support 2 I²C Slave Addresses (0x0F &

0x1F) selected through boot-strap pin (INT)

● CSI-2 TX Interface (This function is supported

only by TC358840XBG )

● Audio Output Interface

 MIPI CSI-2 compliant (Version 1.01 Revision

0.04 – 2 April 2009)

 Dual links CSI-2 (CSI0 and CSI1), each link

supports 4 data lanes @ 1 Gbps/data lane

- CSI0 carries the left half data of HDMI Rx

 Up to four I2S data lines for supporting

multi-Channel audio data (5.1 and 7.1)

 Maximum audio sample frequency supported is

192 kHz @8 CH

 Support 16, 18, 20 or 24-bit data (depend on

Toshiba Electronic Devices & Storage Corporation

1 / 21

2017-10-24

Rev. 1.53

12 3 4 5 6 7...21

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