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TC358766XBG PDF预览

TC358766XBG

更新时间: 2023-12-06 20:13:20
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
22页 498K
描述
Not Recommended for New Design

TC358766XBG 数据手册

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TC358766XBG  
CMOS Digital Integrated Circuit Silicon Monolithic  
TC358766XBG  
Mobile Peripheral Devices  
TC358766XBG  
Overview  
The DSI/DPI to DisplayPortTM converter TC358766XBG is a bridge  
device that enables video streaming from a Host (application or  
baseband processor) over MIPI® DSI or DPI link to drive  
DisplayPortTM display panels.  
P-VFBGA120-0606-0.50AZ  
Weight: 62mg (Typ.)  
Features  
● Translates MIPI® DSI/DPI Link video stream from  
Host to DisplayPortTM Link data to external display  
devices.  
DPI Receiver: Supports one DPI Interface  
between TC358766XBG and Host.  
● The inputs are driven by a DSI Host with 4-Data  
Lanes, upto1 Gbps/lane or DPI Host with 16/18/24  
bit interface upto154 MHz parallel clock.  
● Supports HDCP Digital Content Protection version  
1.3 (DisplayPortTM amendment Rev1.1).  
● The output Interface consists of a DisplayPortTM Tx  
with a 2-lane Main Link and AUX-Ch.  
Up to 16 / 18 / 24 bit parallel data interface.  
Maximum speed at 154 MPs (MPixel per sec).  
Video input data formats: RGB-565, RGB-666  
and RGB-888.  
Only Progressive mode supported.  
Shutdown support (can be used in non-DPI  
mode also).  
● Register Configuration: From DSI link, SPI or I2C  
interface (only one of the SPI and I2C interfaces  
can be active at any time).  
DisplayPortTM Interface: Supports a  
DisplayPortTM link from TC358766XBG to display  
panels.  
● Internally generated H/VSync in DSI mode can be  
muxed out to Host.  
● Interrupt to host to inform any error status or status  
needing attention from Host.  
● Internal test pattern (color bar) generator for DP  
o/p testing without any video (DSI/DPI) i/p.  
● Debug/Test Port: I2C Slave  
High speed serial bridge chip using VESA  
DisplayPortTM 1.1a Standard.  
Supports one dual-lane DisplayPortTM port for  
high bandwidth applications  
Supports up to two (2) single-lane ports for  
connection to two DisplayPortTM panels.  
Support 1.62 or 2.7 Gbps/lane data rate with  
voltage swings @0.4, 0.6, 0.8 or 1.2V  
Support of pre-emphasis levels of 0, 3.5dB and  
6dB.  
Supports Audio related Secondary Data Packets  
AUX channel supported at 1 Mbps.  
HPD support through GPIO[1:0] based  
interrupts  
DSI Receiver: Supports one DSI Interface  
between TC358766XBG and Host.  
MIPI® DSI: v1.01 / MIPI® D-PHY: v0.90  
Compliant.  
Up to four (4) Data Lanes with Bi-direction  
support on Data Lane 0.  
Maximum speed at 1 Gbps/lane.  
Supports Burst as well as Non-Burst Mode  
Video Data.  
- Video data packets are limited to one row per  
Hsync period.  
Enhanced mode supported for HDCP content  
protection.  
Support HDCP encryption Version 1.3 with  
DisplayPortTM amendment Revision 1.1. (on  
DisplayPortTM0 in case two port configuration is  
used)  
Supports video stream packets for video data  
transmission.  
Supports generic long packets for accessing the  
chip’s register set.  
Stream Policy Maker is assumed handled by the  
Host (software/firmware).  
- Start Link training in response to HPD & read  
final Link training status  
- Configure DP link for actual video streaming &  
start video streaming  
Video input data formats:  
- RGB-565, RGB-666 and RGB-888.  
- New DSI V1.02 Data Type Support: 16-bit  
YCbCr 422  
Interlaced video mode is not supported.  
© 2014-2018  
Toshiba Electronic Devices & Storage Corporation  
1 / 22  
2018-05-28  
Rev. 1.1  

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