5秒后页面跳转
捷配首页

Datasheet > TC358774XBG
TC358774XBG PDF预览

TC358774XBG

更新时间： 2024-10-03 14:55:11
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
24页 391K
描述
tablet / Ultrabook™

阅读下载

中文翻译

获取价格

TC358774XBG 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TFBGA,Reach Compliance Code：unknown
Factory Lead Time：16 weeks风险等级：5.11
JESD-30 代码：S-PBGA-B49长度：5 mm
端子数量：49最高工作温度：85 °C
最低工作温度：-30 °C封装主体材料：PLASTIC/EPOXY
封装代码：TFBGA封装形状：SQUARE
封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
座面最大高度：1.2 mm最大供电电压：1.3 V
最小供电电压：1.1 V标称供电电压：1.2 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子形式：BALL
端子节距：0.65 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5 mm
uPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUITBase Number Matches：1

TC358774XBG 数据手册

 浏览型号TC358774XBG的Datasheet PDF文件第2页浏览型号TC358774XBG的Datasheet PDF文件第3页浏览型号TC358774XBG的Datasheet PDF文件第4页浏览型号TC358774XBG的Datasheet PDF文件第5页浏览型号TC358774XBG的Datasheet PDF文件第6页浏览型号TC358774XBG的Datasheet PDF文件第7页 
TC358774XBG/TC358775XBG  
CMOS Digital Integrated Circuit Silicon Monolithic  
TC358774XBG/TC358775XBG  
Mobile Peripheral Devices  
TC358774XBG  
Overview  
The TC358774XBG/TC358775XBG Functional Specification defines  
operation of the DSISM to LVDS low power chip (or more abbreviated,  
TC358775XBG chip). TC358775XBG is the follow-up chip of  
TC358764XBG/ TC358765XBG, which:  
P-VFBGA49-0505-0.65-001  
Weight: 39 mg (Typ.)  
1. Is pin compatible to TC358764XBG/TC358765XBG  
2. Exhibit LVDS Tx block operates at 1.8V @135 MHz to reduce  
operation power  
TC358775XBG  
3. Update 4-lane DSI Rx max bit rate @ 1 Gbps/lane to support  
1920×1200×24 @60fps  
4. Add STBY pin with to enable turning on VDDIO power first before  
other power supplies.  
P-VFBGA64-0606-0.65-001  
Weight: 55 mg (Typ.)  
The primary function of this chip is DSI-to-LVDS Bridge, enabling  
video streaming output over DSI link to drive LVDS-compatible  
display panels. The chip supports up to 1600×1200 24-bits per pixel resolution for single-link LVDS and  
up to WUXGA (1920×1200 24-bits pixels) resolution for dual-link LVDS. As a secondary function, the  
chip also supports an I2C Master which is controlled by the DSI link; this may be used as an interface to  
any other control functions through I2C.  
Features  
● DSI Receiver  
Configurable 1- up to 4-Data-Lane DSI Link with  
Supports display up to 1600×1200 24-bits per  
pixel resolution for single-link, or up to 1920×1200  
24-bits resolutions for dual-link  
bi-directional support on Data Lane 0  
Supports the following pixel formats:  
- RGB666 18-bits per pixel  
- RGB888 24-bits per pixel  
Features Toshiba Magic Square algorithm which  
enables a RGB666 display panel to produce a  
display quality almost equivalent to that of an  
RGB888 24-bits panel  
Maximum bit rate of 1 Gbps/lane  
Video input data formats:  
- RGB565 16-bits per pixel  
- RGB666 18-bits per pixel  
- RGB666 loosely packed 24-bits per pixel  
- RGB888 24-bits per pixel  
Video frame size:  
Flexible mapping of parallel data input bit ordering  
Supports programmable clock polarity  
Supports two power saving states  
- Up to 1600×1200 24-bits per pixel resolution to  
single-link LVDS display panel, limited by 135  
MHz LVDS speed  
- Sleep state, when receiving DSI ULPS signaling  
- Standby state, entered by STBY pin assertion  
- Up to WUXGA resolutions (1920×1200 24-bits  
pixels) to dual-link LVDS display panel, limited by  
4 Gbps DSI link speed  
● System Operation  
Supports Video Stream packets for video data  
Host configures the chip through DSI link  
transmission.  
Through DSI link, Host accesses the chip register  
set using Generic Write and Read packets. One  
Generic Long Write packet can write to multiple  
contiguous register addresses  
Includes an I2C Master function which is controlled  
by Host through DSI link (multi-master is not  
supported)  
Supports generic long packets for accessing the  
chip's register set  
Supports the path for Host to control the on-chip  
I2C Master  
● LVDS FPD Link Transmitter  
Supports single-link or dual-link  
Maximum pixel clock frequency of 135 MHz.  
Maximum pixel clock speed of 135 MHz for single-  
Power management features to save power  
Configuration registers is also accessible through  
I2C Slave interface  
link or 270 MHz for dual-link  
© 2014-2020  
Toshiba Electronic Devices & Storage Corporation  
1 / 24  
2020-12-16  
Rev.1.9.2  
1234567...24

中文翻译

下载PDF

与TC358774XBG相关器件

型号 品牌 获取价格 描述 数据表
TC358775XBG TOSHIBA

获取价格

 		Mobile Peripheral Bridge Chip IC
TC358777XBG TOSHIBA

获取价格

 		tablet / Ultrabook™
TC358778XBG TOSHIBA

获取价格

 		CMOS Digital Integrated Circuit Silicon Monolithic
TC358779XBG TOSHIBA

获取价格

 		Mobile Peripheral Bridge Chip IC
TC358840XBG TOSHIBA

获取价格

 		digital media adapter (DMA) / smart monitor / smart set-top box / smart TV
TC35885TB TOSHIBA

获取价格

 		IC MUX/DEMUX, PBGA256, 27 X 27 MM, 1.27 MM PITCH, NON CONDUCTIVE TIE BAR, TBGA-256, ATM/SO
TC358860XBG TOSHIBA

获取价格

 		Bridge Chip IC
TC358867XBG TOSHIBA

获取价格

 		tablet / Ultrabook™ / information terminal
TC358867XBG(EL) TOSHIBA

获取价格

 		Consumer Circuit, CMOS, PBGA80
TC358870XBG TOSHIBA

获取价格

 		Mobile Peripheral Bridge Chip IC

与TC358774XBG相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证