TC358870XBG
CMOS Digital Integrated Circuit Silicon Monolithic
TC358870XBG
TC358870XBG
Overview
Mobile Peripheral Devices
TC358870XBG, Ultra HD to DSI, bridge converts high resolution (higher
than 4 Gbps) HDMI® stream to MIPI® DSI Tx video. It is a follow up device
of TC358779XBG, without scalar functionality. The HDMI-RX runs at 297
MHz to carry up to 7.2 Gbps video stream. It requires dual link MIPI DSI Tx,
1 Gbps/data lane, to transmit out a maximum 7.2 Gbps video data.
P-VFBGA80-0707-0.65-001
Weight: 67 mg (Typ.)
The bridge chip is necessary for current and next generation Application Processors to drive a (dual) DSI link
display by using its HDMI Tx output port.
Features
2048-pixel plus up to full length overlap, DSI0
data length could be different from that of DSI1's
- The maximum Hsync skew between DSI0 and
DSI1 can be less than 10 ByteClk
● HDMI-RX Interface
HDMI 1.4b
- Video Formats Support (Up to 4K×2K / 30fps),
maximum 24 bps (bit-per-pixel) no deep color
support
RGB, YCbCr444: 24-bpp
YCbCr422: 24-bpp
- Color Conversion
4:2:2 to 4:4:4 is supported
4:4:4: to 4:2:2 is supported
Single link DSI, maximum horizontal pixel width
- 2558 pixels (24-bit per pixel)
- 3411 pixels (16-bit per pixel)
Supports video data formats
- RGB666, RGB888, YCbCr444, YCbCr 422
16-bit and YCbCr 422 24-bit
- YCbCr inputs can be converted into RGB before
outputting
RGB888 to YCbCr (4:4:4 / 4:2:2) is supported
YCbCr (4:4:4 / 4:2:2) to RGB888/666 is
supported
● I2C Interface
Note: for RGB666 (R=R[5:0],2'b00,
G=G[5:0],2'b00, B=G[5:0],2'b00)
- Maximum HDMI clock speed: 297 MHz
- Audio Supports
Internal Audio PLL to track N/CTS value
transmitted by the ACR packet.
- 3D Support
- Support HDCP1.4 decryptions
- EDID Support, Release A, Revision 1 (Feb 9,
2000)
Support for normal (100 kHz), fast mode (400 kHz)
and ultrafast mode (2 MHz)
Slave Mode
- To be used by an external Master to configure all
TC358870XBG internal registers, including
EDID_SRAM and panel control
- Support 2 I2C Slave Addresses (0x0F & 0x1F)
selected through boot-strap pin (INT)
First 128 byte (EDID 1.3 structure)
First E-EDID Extension: 128 bytes of CEA
Extension version 3 (specified in CEA-861-D)
Embedded 1K-byte SRAM (EDID_SRAM)
Does not support Audio Return Path and HDMI
Ethernet Channels
● Audio Output Interface
Up to four I2S data lines for supporting
multi-Channel audio data (5.1 and 7.1)
Maximum audio sample frequency supported is 192
kHz @8 CH
Support 16, 18, 20 or 24-bit data (depend on HDMI
input stream)
● DSI TX Interface
Support Master Clock output only
Support 32 bit-wide time-slot only
Output Audio Over Sampling clock (256fs)
Either I2S or TDM Audio interface available (pins
are multiplexed)
MIPI DSI compliant (Version 1.1 22 November
2011)
Dual links DSI (DSI0 and DSI1), each link supports
4 data lanes @1 Gbps/ data lane
- DSI0 carries the left half data of HDMI Rx video
stream and DSI1 carries the right one at the
default configuration.
- Left or right data can be assigned/programmed to
either DSI Tx link
I2S Audio Interface
- Support Left or Right-justify with MSB first
TDM (Time Division Multiplexed) Audio Interface
- Fixed to 8 channels (depend on HDMI input
stream)
- The maximum length of each half is limited to
1
2016-04-01
© 2014 Toshiba Corporation