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TC358775XBG PDF预览

TC358775XBG

更新时间： 2024-10-02 20:02:35
品牌 Logo 应用领域
东芝 - TOSHIBA 外围集成电路
页数 文件大小 规格书
26页 993K
描述
Mobile Peripheral Bridge Chip IC

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中文翻译

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TC358775XBG 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TFBGA,Reach Compliance Code：unknown
风险等级：5.63JESD-30 代码：S-PBGA-B64
长度：6 mm端子数量：64
最高工作温度：85 °C最低工作温度：-30 °C
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装形状：SQUARE封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED座面最大高度：1.2 mm
最大供电电压：1.3 V最小供电电压：1.1 V
标称供电电压：1.2 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子形式：BALL端子节距：0.65 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUIT
Base Number Matches：1

TC358775XBG 数据手册

 浏览型号TC358775XBG的Datasheet PDF文件第2页浏览型号TC358775XBG的Datasheet PDF文件第3页浏览型号TC358775XBG的Datasheet PDF文件第4页浏览型号TC358775XBG的Datasheet PDF文件第5页浏览型号TC358775XBG的Datasheet PDF文件第6页浏览型号TC358775XBG的Datasheet PDF文件第7页 
TC358774XBG/TC358775XBG  
CMOS Digital Integrated Circuit Silicon Monolithic  
TC358774XBG, TC358775XBG  
Mobile Peripheral Devices  
TC358774XBG  
Overview  
The TC358774XBG/TC358775XBG Functional Specification defines  
operation of the DSI TO LVDS low power chip (or more abbreviated,  
TC358775XBG chip). 775XBG is the follow-up chip of TC358764XBG/  
TC35865XBG, which:  
P-VFBGA49-0505-0.65-001  
Weight: 31 mg (Typ.)  
1. Is pin compatible to TC358764XBG/TC358765XBG  
2. Exhibit LVDS Tx block operates at 1.8V @135 MHz to reduce operation  
power  
TC358775XBG  
3. Update 4-lane DSI Rx max bit rate @ 1 Gbps/lane to support  
1920×1200×24 @60fps  
4. Add STBY pin with to enable turning on VDDIO power first before other  
power supplies.  
P-VFBGA64-0606-0.65-001  
Weight: 47 mg (Typ.)  
The primary function of this chip is DSI-to-LVDS Bridge, enabling video  
streaming output over DSI link to drive LVDS-compatible display panels.  
The chip supports up to 1600×1200 24-bit pixel resolution for single-link LVDS and up to WUXGA (1920×1200  
24-bit pixels) resolution for dual-link LVDS. As a secondary function, the chip also supports an I2C Master which  
is controlled by the DSI link; this may be used as an interface to any other control functions through I2C.  
Features  
● DSI Receiver  
Configurable 1- up to 4-Data-Lane DSI Link with  
Supports display up to 1600×1200 24-bit/pixel  
resolution for single-link, or up to 1920×1200 24-bit  
resolutions for dual-link  
bi-directional support on Data Lane 0  
Maximum bit rate of 1 Gbps/lane  
Video input data formats:  
- RGB565 16 bits per pixel  
- RGB666 18 bits per pixel  
- RGB666 loosely packed 24 bits per pixel  
- RGB888 24 bits per pixel  
Video frame size:  
Supports the following pixel formats:  
- RGB666 18 bits per pixel  
- RGB888 24 bits per pixel  
Features Toshiba Magic Square algorithm which  
enables a RGB666 display panel to produce a  
display quality almost equivalent to that of an  
RGB888 24-bit panel  
- Up to 1600×1200 24-bit/pixel resolution to single-  
link LVDS display panel, limited by 135 MHz  
LVDS speed  
Flexible mapping of parallel data input bit ordering  
Supports programmable clock polarity  
Supports two power saving states  
- Sleep state, when receiving DSI ULPS signaling  
- Standby state, entered by STBY pin assertion  
- Up to WUXGA resolutions (1920×1200 24-bit  
pixels) to dual-link LVDS display panel, limited by  
4 Gbps DSI link speed  
Supports Video Stream packets for video data  
● System Operation  
Host configures the chip through DSI link  
transmission.  
Supports generic long packets for accessing the  
Through DSI link, Host accesses the chip register  
set using Generic Write and Read packets. One  
Generic Long Write packet can write to multiple  
contiguous register addresses  
chip's register set  
Supports the path for Host to control the on-chip  
I2C Master  
Includes an I2C Master function which is controlled  
by Host through DSI link (multi-master is not  
supported)  
● LVDS FPD Link Transmitter  
Supports single-link or dual-link  
Maximum pixel clock frequency of 135 MHz.  
Power management features to save power  
Maximum pixel clock speed of 135 MHz for single-  
link or 270 MHz for dual-link  
Configuration registers is also accessible through  
I2C Slave interface  
1 / 26  
2016-02-18  
© 2014 Toshiba Corporation  
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中文翻译

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