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TC358748XBG PDF预览

TC358748XBG

更新时间: 2024-10-03 14:56:55
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
19页 358K
描述
industrial device / smartphone / tablet / VOIP phone

TC358748XBG 技术参数

是否Rohs认证: 符合生命周期:Unknown
包装说明:VFBGA-80Reach Compliance Code:unknown
Factory Lead Time:16 weeks风险等级:5.62
Base Number Matches:1

TC358748XBG 数据手册

 浏览型号TC358748XBG的Datasheet PDF文件第2页浏览型号TC358748XBG的Datasheet PDF文件第3页浏览型号TC358748XBG的Datasheet PDF文件第4页浏览型号TC358748XBG的Datasheet PDF文件第5页浏览型号TC358748XBG的Datasheet PDF文件第6页浏览型号TC358748XBG的Datasheet PDF文件第7页 
TC358746AXBG/TC358748XBG  
CMOS Digital Integrated Circuit Silicon Monolithic  
TC358746AXBG/TC358748XBG  
Mobile Peripheral Devices  
TC358746AXBG  
Overview  
The MIPI® CSI-2 to Parallel port and Parallel port to CSI-2  
(TC358746AXBG/TC358748XBG) is a bridge device that converts  
MIPI data transfers from devices such as a camera to an application  
processor over a Parallel port interface. All internal registers can be  
access through I2C or SPI (in CSI out case only).  
P-VFBGA72-0404-0.40A3  
Weight: 32 mg (Typ.)  
TC358748XBG  
Features  
CSI-2 TX/RX Interface  
MIPI CSI-2 compliant (Version 1.01 Revision  
P-VFBGA80-0707-0.65-001  
Weight: 68 mg (Typ.)  
0.04 – 2 April 2009)  
Configurable to TX or RX controller  
Supports up to 1Gbps per data lane  
Supports up to 4 data lanes  
Supports video data formats  
- RX: RAW8/10/12/14, YUV422 (CCIR/ITU 8/10-  
bit), RGB888/666/565 and User-Defined 8-bit  
GPIO signals  
3 GPIO signals  
- Three GPIO signals can be configured as  
control signals (MCLK, CXRST, XShutdown) for  
CSI-2 RX device.  
- Or one GPIO signal can be configured as INT  
signal for Parallel interface.  
- TX: YUV422 (CCIR/ITU 8/10-bit), YUV444,  
RGB888/666/565 and RAW8/10/12/14  
Parallel Port Interface  
Supports data formats  
System  
Clock and power management support to  
achieve low power states.  
- 24-bit bus – un-packed format (Both Input and  
Output mode)  
RGB888/666/565, RAW8/10/12/14 and  
YUV422 8-bit (on 8/16-bit data bus) and 10-bit  
data formats.  
Power supply inputs  
Core and MIPI D-PHY: 1.2 V  
I/O: 1.8 V – 3.3 V  
YUV444 (Parallel Input mode only)  
- YUV422 8-bit – ITU BT.656 and ITU BT.601  
(Parallel input mode only)  
Up to 100 MHz PCLK frequency for Output  
mode, and 166 MHz for Input mode.  
I2C Slave Interface (CS = L)  
Support for normal (100 kHz), fast mode (400  
kHz) and special mode (1 MHz)  
Configure all TC358746AXBG/TC358748XBG  
internal registers  
SPI Slave Interface (Only applicable in CSIOut  
configuration, MSEL = H, and CS = H)  
SPI interface support for up to 25 MHz  
operation.  
Configure all TC358746AXBG/TC358748XBG  
internal registers  
© 2014-2020  
Toshiba Electronic Devices & Storage Corporation  
1 / 19  
2020-12-14  
Rev.1.85  

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