Datasheet > STP2200ABGA

STP2200ABGA

更新时间： 2024-11-26 06:14:51

品牌	Logo	应用领域
其他 - ETC		控制器
页数	文件大小	规格书
36页	411K
描述
Uniprocessor System Controller

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数据手册

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STP2200ABGA 数据手册

STP2200ABGA

July 1997

USC

Uniprocessor System Controller

DATA SHEET

DESCRIPTION

The Uniprocessor System Controller (USC) has a DRAM memory controller and functions to regulate the

ﬂow of requests and data on the UPA bus. It also controls the resets going to all UPA clients.

Features

Beneﬁts

• Controls up to eight standard SS-10/SS-20-type DRAM

SIMMs

• Standard workstation memory

• Supports various memory SIMM organizations: 16 MB, 64

MB, and 256 MB as well as dual-stacked 128-MB SIMMs

• Flexibility

• Controls and generates a number of resets for the system

• High integration

• Programmed via a standard 8-bit asynchronous interface

(EBus)

• Allows design of low-cost, low-chip-count embedded

systems

• JTAG interface allows full chip scan

• 225-pin ABGA package

• Ease of design and testability

• Low cost

The USC is used as the system controller of a complete Uniprocessor UltraSPARC system.

Note: Instead of using the U2S, the USC can also be used with the UPA to PCI-bus; I/O interface

controller (U2P)

UPA Devices

Abbreviations

SC_UP

RISC

Part Number

STP 2200ABGA

STP2210QFP

STP2220ABGA

STP2222ABGA

STP2230SOP

Description

Uniprocessor System Controller

USC

RIC

U2S

U2P

XBI

Reset/Interrupt/Clock Controller

UPA to SBus I/O interface controller

UPA to PCI bus I/O Interface controller

Crossbar Data Path

SYSIO

Psycho

BMX

Note: This data sheet refers to the UPA to System I/O interface. The UPA to PCI bus Interface controller

(U2P) can be substituted where U2S appears.

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