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SN74LVC2G74-Q1_15 PDF预览

SN74LVC2G74-Q1_15

更新时间： 2024-02-08 10:41:32
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德州仪器 - TI /
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10页 154K
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SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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SN74LVC2G74-Q1_15 数据手册

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SN74LVC2G74-Q1  
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
www.ti.com  
SCES563B–MARCH 2004–REVISED AUGUST 2006  
FEATURES  
•
Qualification in Accordance With  
AEC-Q100  
•
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
(1)  
•
•
Qualified for Automotive Applications  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Customer-Specific Configuration Control Can  
Be Supported Along With Major-Change  
Approval  
– 1000-V Charged-Device Model (C101)  
•
•
•
•
•
•
Supports 5-V VCC Operation  
DCU PACKAGE  
(TOP VIEW)  
Inputs Accept Voltages to 5.5 V  
Max tpd of 6.9 ns at 3.3 V  
VCC  
PRE  
CLR  
Q
1
2
3
4
8
7
6
5
CLK  
D
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
Q
Typical VOLP (Output Ground Bounce) <0.8 V  
GND  
at VCC = 3.3 V, TA = 25°C  
•
•
Typical VOHV (Output VOH Undershoot) >2 V at  
VCC = 3.3 V, TA = 25°C  
Ioff Supports Partial-Power-Down Mode  
Operation  
(1) Contact factory for details. Q100 qualification data available  
on request.  
DESCRIPTION/ORDERING INFORMATION  
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.  
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input can be changed without affecting the levels at the outputs.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
C74_  
–40°C to 125°C  
VSSOP – DCU Reel of 3000  
SN74LVC2G74QDCURQ1  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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