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SN74LVC2G80DCTRG4 PDF预览

SN74LVC2G80DCTRG4

更新时间： 2024-11-05 11:07:11
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德州仪器 - TI 触发器锁存器
页数 文件大小 规格书
13页 276K
描述
双路正边沿触发式 D 型触发器 | DCT | 8 | -40 to 125

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SN74LVC2G80DCTRG4 数据手册

 浏览型号SN74LVC2G80DCTRG4的Datasheet PDF文件第2页浏览型号SN74LVC2G80DCTRG4的Datasheet PDF文件第3页浏览型号SN74LVC2G80DCTRG4的Datasheet PDF文件第4页浏览型号SN74LVC2G80DCTRG4的Datasheet PDF文件第5页浏览型号SN74LVC2G80DCTRG4的Datasheet PDF文件第6页浏览型号SN74LVC2G80DCTRG4的Datasheet PDF文件第7页 
SN74LVC2G80  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
www.ti.com  
SCES309C–DECEMBER 2001–REVISED JUNE 2005  
FEATURES  
DCT OR DCU PACKAGE  
(TOP VIEW)  
•
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
•
•
•
•
•
Supports 5-V VCC Operation  
1CLK  
1D  
2Q  
GND  
V
CC  
1
2
3
4
8
7
6
5
1Q  
2D  
2CLK  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.2 ns at 3.3 V  
Low Power Consumption, 10-µA Max ICC  
Typical VOLP (Output Ground Bounce)  
< 0.8 V at VCC = 3.3 V, TA = 25°C  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
•
•
•
•
Typical VOHV (Output VOH Undershoot)  
> 2 V at VCC = 3.3 V, TA = 25°C  
4
3
2
1
5
6
7
8
GND  
2Q  
2CLK  
2D  
Ioff Feature Supports Partial-Power-Down  
Mode Operation  
1D  
1CLK  
1Q  
V
Latch-Up Performance Exceeds 100 mA  
Per JESD 78, Class II  
CC  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.  
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the  
positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the  
rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting  
the levels at the outputs.  
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YEP  
SN74LVC2G80YEPR  
Tape and reel  
_ _ _CX_  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SN74LVC2G80YZPR  
–40°C to 85°C  
SSOP – DCT  
Tape and reel SN74LVC2G80DCTR  
Tape and reel SN74LVC2G80DCUR  
C80_ _ _  
C80_  
VSSOP – DCU  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2001–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...13

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SN74LVC2G80DCTRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC2G80DCTR TI

完全替代

 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

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