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SN74LVC2G80_08 PDF预览

SN74LVC2G80_08

更新时间: 2024-01-19 07:07:11
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德州仪器 - TI 触发器
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14页 459K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

SN74LVC2G80_08 数据手册

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SN74LVC2G80  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
www.ti.com  
SCES309EDECEMBER 2001REVISED FEBRUARY 2007  
FEATURES  
Available in the Texas Instruments  
NanoFree™ Package  
>2 V at VCC = 3.3 V, TA = 25°C  
Ioff Feature Supports Partial-Power-Down  
Mode Operation  
Supports 5-V VCC Operation  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.2 ns at 3.3 V  
Latch-Up Performance Exceeds 100 mA  
Per JESD 78, Class II  
ESD Protection Exceeds JESD 22  
Low Power Consumption, 10-µA Max ICC  
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
Typical VOHV (Output VOH Undershoot)  
1000-V Charged-Device Model (C101)  
DCT PACKAGE  
(TOP VIEW)  
DCU PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
4 5  
GND  
2Q  
2CLK  
VCC  
1Q  
1
2
3
4
8
7
6
5
1CLK  
1D  
VCC  
1Q  
1
2
3
4
8
7
6
5
1CLK  
1D  
3 6  
2 7  
1 8  
2D  
1Q  
VCC  
1D  
2Q  
2D  
1CLK  
GND  
2CLK  
2Q  
2D  
GND  
2CLK  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.  
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the  
positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the  
rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without  
affecting the levels at the outputs.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
Reel of 3000  
SN74LVC2G80YZPR  
_ _ _CX_  
–40°C to 85°C  
SSOP – DCT  
Reel of 3000  
Reel of 3000  
SN74LVC2G80DCTR  
SN74LVC2G80DCUR  
C80_ _ _  
C80_  
VSSOP – DCU  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2001–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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