5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 触发器/锁存器> SN74LVC2G79
SN74LVC2G79 PDF预览

SN74LVC2G79

更新时间： 2024-02-22 06:41:18
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
13页 279K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

阅读下载

中文翻译

获取价格

SN74LVC2G79 数据手册

 浏览型号SN74LVC2G79的Datasheet PDF文件第2页浏览型号SN74LVC2G79的Datasheet PDF文件第3页浏览型号SN74LVC2G79的Datasheet PDF文件第4页浏览型号SN74LVC2G79的Datasheet PDF文件第5页浏览型号SN74LVC2G79的Datasheet PDF文件第6页浏览型号SN74LVC2G79的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢂꢉ  
ꢍ
ꢊ
ꢋ
ꢌ
ꢄ
ꢍ
ꢎ
ꢀ
ꢏ
ꢐ
ꢏ
ꢅ
ꢑ
ꢒ
ꢑ
ꢊ
ꢈ
ꢑ
ꢒ
ꢐ
ꢓ
ꢏ
ꢈ
ꢈ
ꢑ
ꢓ
ꢑ
ꢊ
ꢊ
ꢒ
ꢐ
ꢔ
ꢑ
ꢕ
ꢄ
ꢏ
ꢍ
ꢒ
ꢕ
ꢄ
ꢎ
ꢍ
SCES498B − OCTOBER 2003 − REVISED DECEMBER 2003  
DCT OR DCU PACKAGE  
(TOP VIEW)  
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Supports 5-V V Operation  
D
D
D
D
D
D
CC  
1CLK  
1D  
2Q  
GND  
V
CC  
1Q  
2D  
2CLK  
1
2
3
4
8
7
6
5
Inputs Accept Voltages to 5.5 V  
Max t of 4.2 ns at 3.3 V  
pd  
Low Power Consumption, 10-µA Max I  
CC  
24-mA Output Drive at 3.3 V  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
4 5  
3 6  
2 7  
1 8  
GND  
2Q  
1D  
2CLK  
2D  
1Q  
D
D
D
D
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
>2 V at V  
= 3.3 V, T = 25°C  
CC  
A
I
Feature Supports Partial-Power-Down  
off  
1CLK  
V
CC  
Mode Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V  
operation.  
CC  
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on  
the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related  
to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without  
affecting the levels at the outputs.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
‡
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
SN74LVC2G79YEPR  
SN74LVC2G79YZPR  
Tape and reel  
_ _ _CR_  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
−40°C to 85°C  
SSOP − DCT  
Tape and reel  
Tape and reel  
SN74LVC2G79DCTR  
SN74LVC2G79DCUR  
C79_ _ _  
C79_  
VSSOP − DCU  
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one  
following character to designate the assembly/test site. Pin  
1 identifier indicates solder-bump composition  
(1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
ꢍ
ꢍ
ꢓ
ꢎ
ꢥ
ꢊ
ꢠ
ꢋ
ꢆ
ꢞ
ꢐ
ꢟ
ꢏ
ꢙ
ꢎ
ꢗ
ꢁ
ꢘ
ꢊ
ꢌ
ꢐ
ꢌ
ꢖ
ꢗ
ꢡ
ꢘ
ꢙ
ꢟ
ꢚ
ꢛ
ꢜ
ꢜ
ꢝ
ꢝ
ꢖ
ꢖ
ꢙ
ꢙ
ꢗ
ꢗ
ꢖ
ꢞ
ꢞ
ꢢ
ꢟ
ꢠ
ꢚ
ꢚ
ꢡ
ꢡ
ꢗ
ꢝ
ꢜ
ꢛ
ꢞ
ꢞ
ꢙ
ꢘ
ꢢ
ꢐꢡ  
ꢠ
ꢣ
ꢞ
ꢤ
ꢖ
ꢟ
ꢜ
ꢞ
ꢝ
ꢖ
ꢝ
ꢙ
ꢚ
ꢗ
ꢠ
ꢥ
ꢜ
ꢗ
ꢝ
ꢝ
ꢡ
ꢞ
ꢦ
Copyright 2003, Texas Instruments Incorporated  
ꢚ
ꢙ
ꢟ
ꢝ
ꢙ
ꢚ
ꢛ
ꢝ
ꢙ
ꢞ
ꢢ
ꢖ
ꢘ
ꢖ
ꢟ
ꢡ
ꢚ
ꢝ
ꢧ
ꢝ
ꢡ
ꢚ
ꢙ
ꢘ
ꢨ
ꢜ
ꢏ
ꢗ
ꢛ
ꢡ
ꢞ
ꢝ
ꢜ
ꢗ
ꢥ
ꢜ
ꢚ
ꢥ
ꢩ
ꢜ
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ  
ꢚ
ꢚ
ꢜ
ꢗ
ꢝ
ꢪ
ꢦ
ꢍ
ꢚ
ꢙ
ꢥ
ꢠ
ꢟ
ꢝ
ꢖ
ꢙ
ꢗ
ꢢ
ꢚ
ꢙ
ꢟ
ꢡ
ꢞ
ꢞ
ꢖ
ꢗ
ꢫ
ꢥ
ꢙ
ꢡ
ꢞ
ꢗ
ꢙ
ꢝ
ꢗ
ꢡ
ꢟ
ꢡ
ꢞ
ꢞ
ꢜ
ꢚ
ꢖ
ꢤ
ꢪ
ꢖ
ꢗ
ꢟ
ꢤ
ꢠ
ꢥ
ꢡ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

中文翻译

下载PDF

与SN74LVC2G79相关器件

型号 品牌 获取价格 描述 数据表
SN74LVC2G79_08 TI

获取价格

 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74LVC2G79DCTR TI

获取价格

 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74LVC2G79DCTRE4 TI

获取价格

 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74LVC2G79DCUR TI

获取价格

 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74LVC2G79DCURE4 TI

获取价格

 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74LVC2G79DCURG4 TI

获取价格

 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74LVC2G79YEPR TI

获取价格

 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74LVC2G79YZPR TI

获取价格

 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74LVC2G80 TI

获取价格

 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74LVC2G80_08 TI

获取价格

 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

与SN74LVC2G79相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证