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SN74LVC2G74-EP

更新时间： 2024-11-04 12:15:07
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
12页 451K
描述
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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SN74LVC2G74-EP 数据手册

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SN74LVC2G74-EP  
www.ti.com ....................................................................................................................................................................................................... SCES718–MAY 2008  
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
1
FEATURES  
•
Controlled Baseline  
•
•
•
•
•
Inputs Accept Voltages to 5.5 V  
Max tpd of 7.9 ns at 3.3 V  
–
–
–
One Assembly Site  
One Test Site  
Low Power Consumption, 10 µA Max ICC  
±24 mA Output Drive at 3.3 V  
One Fabrication Site  
•
•
Extended Temperature Performance of –55°C  
to 125°C  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
Enhanced Diminishing Manufacturing Sources  
(DMS) Support  
•
•
•
•
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
•
•
•
Enhanced Product-Change Notification  
Ioff Supports Partial Power Down Mode  
Operation  
(1)  
Qualification Pedigree  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Supports 5-V VCC Operation  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
ESD Protection Exceeds JESD 22  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
1000-V Charged-Device Model (C101)  
DCU PACKAGE  
(TOP VIEW)  
VCC  
PRE  
CLR  
Q
1
2
3
4
8
7
6
5
CLK  
D
Q
GND  
DESCRIPTION/ORDERING INFORMATION  
This single positive edge triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.  
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input can be changed without affecting the levels at the outputs.  
This device is fully specified for partial power down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2008, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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