SI7392ADP

更新时间： 2024-11-02 06:11:35

品牌	Logo	应用领域
威世 - VISHAY		开关
页数	文件大小	规格书
3页	235K
描述
N-Channel Reduced Qg, Fast Switching WFET

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SI7392ADP 数据手册

SPICE Device Model Si7392ADP

Vishay Siliconix

N-Channel Reduced Q_g, Fast Switching WFET

CHARACTERISTICS

• N-Channel Vertical DMOS

• Macro Model (Subcircuit Model)

• Level 3 MOS

• Apply for both Linear and Switching Application

• Accurate over the −55 to 125°C Temperature Range

• Model the Gate Charge, Transient, and Diode Reverse Recovery

Characteristics

DESCRIPTION

The attached spice model describes the typical electrical

characteristics of the n-channel vertical DMOS. The subcircuit

model is extracted and optimized over the −55 to 125°C

temperature ranges under the pulsed 0-V to 10-V gate drive. The

saturated output impedance is best fit at the gate bias near the

threshold voltage.

A novel gate-to-drain feedback capacitance network is used to model

the gate charge characteristics while avoiding convergence difficulties

of the switched C_gdmodel. All model parameter values are optimized

to provide a best fit to the measured electrical data and are not

intended as an exact physical interpretation of the device.

SUBCIRCUIT MODEL SCHEMATIC

This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate

data sheet of the same number for guaranteed specification limits.

www.vishay.com

Document Number: 73517

S-61151Rev. B, 26-Jun-06

12 3

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