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PDM4M4110S20Z PDF预览

PDM4M4110S20Z

更新时间: 2024-10-28 20:50:07
品牌 Logo 应用领域
IXYS 静态存储器内存集成电路
页数 文件大小 规格书
10页 215K
描述
SRAM Module, 512KX32, 20ns, CMOS, ZIP-72

PDM4M4110S20Z 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:ZIP
包装说明:ZIP-72针数:72
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.65
最长访问时间:20 nsJESD-30 代码:R-XZMA-T72
内存密度:16777216 bit内存集成电路类型:SRAM MODULE
内存宽度:32功能数量:1
端子数量:72字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX32封装主体材料:UNSPECIFIED
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子位置:ZIG-ZAG处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

PDM4M4110S20Z 数据手册

 浏览型号PDM4M4110S20Z的Datasheet PDF文件第3页浏览型号PDM4M4110S20Z的Datasheet PDF文件第4页浏览型号PDM4M4110S20Z的Datasheet PDF文件第5页浏览型号PDM4M4110S20Z的Datasheet PDF文件第7页浏览型号PDM4M4110S20Z的Datasheet PDF文件第8页浏览型号PDM4M4110S20Z的Datasheet PDF文件第9页 
PRELIMINARY  
PDM4M4110  
AC Electrical Characteristics (Vcc = 5V ± 10%, T = 0°C to +70°C)  
A
PDM4M4110SXXZ, PDM4M4110SXXM  
-15 ns -20 ns -25 ns -35 ns  
Min. Max. Min. Max. Min. Max. Min. Max.  
Symbol  
Parameter  
Unit  
Read Cycle  
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
15  
5
15  
15  
6
20  
3
20  
20  
10  
12  
8
25  
3
25  
25  
12  
14  
10  
25  
35  
3
35  
35  
15  
16  
12  
35  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address Access Time  
AA  
Chip Select Access Time  
ACS  
(1)  
Chip Select to Output inLow-Z  
Output Enable to Output Valid  
Output Enable to Output in Low-Z  
Chip Deselect to Output in High-Z  
Output Disable to Output in High-Z  
Output Hold from Address Change  
Chip Select to Power-Up Time  
Chip Deselect to Power-Down Time  
CLZ  
0
0
0
0
OE  
(1)  
(1)  
10  
6
OLZ  
3
3
3
3
CHZ  
OHZ  
OH  
(1)  
15  
20  
(1)  
0
0
0
0
PU  
PD  
(1)  
Write Cycle  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
15  
13  
13  
3
8
20  
18  
18  
3
25  
20  
20  
3
13  
35  
25  
25  
3
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CW  
AW  
Chip Select to End of Write  
Address Valid to End of Write  
Address Setup Time  
(2)  
AS  
Write Pulse Width  
13  
0
15  
0
8
17  
0
22  
0
WP  
WR  
(2)  
(1)  
Write Recovery Time  
Write Enable to Output in High-Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output Active from End of Write  
10  
0
12  
0
15  
0
20  
0
WHZ  
DW  
(2)  
DH  
(1)  
2
2
2
2
OW  
NOTE 1. This parameter is determined by device characteristics but is not production tested.  
2. t = 0 ns for CS controlled write cycles. t , t = 3 ns for CS controlled write cycles  
AS  
DH WR  
Rev 2.3

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