Datasheet > PDM4M4110S25M

PDM4M4110S25M

更新时间： 2024-02-22 18:45:31

品牌	Logo	应用领域
IXYS		静态存储器
页数	文件大小	规格书
10页	215K
描述
SRAM Module, 512KX32, 25ns, CMOS, SIMM-72

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技术参数
数据手册

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PDM4M4110S25M 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SIMM
包装说明：	,	针数：	72
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.78
Base Number Matches：	1

PDM4M4110S25M 数据手册

PRELIMINARY

PDM4M4110

512K x 32 CMOS

Static RAM Module

The PDM4M4110 is packaged in a 72-pin FR-4 ZIP

(Zig-zag In-line vertical Package) or a 72-pin SIMM

(Single In-line Memory Module). The ZIP conﬁgura-

Features

■ High-density 2 megabyte Static RAM module

■ Low proﬁle 72-pin ZIP (Zig-zag In-line vertical

Package) or 72-pin SIMM (Single In-line Memory

Module)

_{tion allows 72 pins to be placed on a package 3.95"}2

long and 0.250" wide. At only 0.600" high, this low-

proﬁle package is ideal for systems with minimum

board spacing. The SIMM conﬁguration allows use of

■ Fast access time: 15 ns (max.)

■ Surface mounted plastic components on an epoxy

laminate (FR-4) substrate Single 5V (±10%) power

supply

■ Multiple V pins and decoupling capacitors for

maximum noise immunity

■ Inputs/outputs directly TTL compatible

edge mounted sockets to secure the module.

All inputs and outputs of the PDM4M4110 are TTL

compatible and operate from a single 5V supply. Mul-

tiple ground pins and on board decoupling capacitors

provide maximum immunity from noise.

Four identiﬁcation pins (PD0, PD1, PD2, PD3) are pro-

vided for applications in which different density

versions of the module are used. In this way, the tar-

get system can read the respective levels of PD0, PD1,

PD2, PD3 to determine a 512K depth.

Description

The PDM4M4110 is a 512K x 32 static RAM module

constructed on an epoxy laminate (FR-4) substrate

using four (4) 512K x 8 static RAMs in plastic SOJ

packages. Availability of four chip select lines pro-

vides byte access. The PDM4M4110 is available with

access times as fast as 15 ns with minimal power

consumption.

Functional Block Diagram

CS1

CS2

CS3

CS4

A18-A0

PD3-PD0

512K x 32

RAM

I/O31-I/O0

Rev 2.3 - 1/15/96

8-65

12 3 4 5 6 7...10

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