Datasheet > PDM4M4110S25M

PDM4M4110S25M

更新时间： 2024-01-17 15:46:45

品牌	Logo	应用领域
IXYS		静态存储器
页数	文件大小	规格书
10页	215K
描述
SRAM Module, 512KX32, 25ns, CMOS, SIMM-72

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技术参数
数据手册

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PDM4M4110S25M 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SIMM
包装说明：	,	针数：	72
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.78
Base Number Matches：	1

PDM4M4110S25M 数据手册

PRELIMINARY

PDM4M4110

AC Electrical Characteristics (Vcc = 5V ± 10%, T = 0°C to +70°C)

PDM4M4110SXXZ, PDM4M4110SXXM

-15 ns -20 ns -25 ns -35 ns

Min. Max. Min. Max. Min. Max. Min. Max.

Symbol

Parameter

Unit

Read Cycle

Read Cycle Time

—

Address Access Time

Chip Select Access Time

ACS

(1)

Chip Select to Output inLow-Z

Output Enable to Output Valid

Output Enable to Output in Low-Z

Chip Deselect to Output in High-Z

Output Disable to Output in High-Z

Output Hold from Address Change

Chip Select to Power-Up Time

Chip Deselect to Power-Down Time

CLZ

—

(1)

—

OLZ

—

CHZ

OHZ

(1)

—

(1)

—

Write Cycle

Write Cycle Time

—

–

—

Chip Select to End of Write

Address Valid to End of Write

Address Setup Time

(2)

Write Pulse Width

—

(2)

(1)

Write Recovery Time

Write Enable to Output in High-Z

Data to Write Time Overlap

Data Hold from Write Time

Output Active from End of Write

—

WHZ

—

(2)

(1)

NOTE 1. This parameter is determined by device characteristics but is not production tested.

2. t = 0 ns for CS controlled write cycles. t , t = 3 ns for CS controlled write cycles

DH WR

8-70

Rev 2.3 - 1/15/96

1...3 4 567 8 9 10

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