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NTMSD3P102R2 PDF预览

NTMSD3P102R2

更新时间： 2024-11-18 03:28:11
品牌 Logo 应用领域
安森美 - ONSEMI 肖特基二极管
页数 文件大小 规格书
10页 123K
描述
P−Channel Enhancement−Mode Power MOSFET and Schottky Diode Dual SO−8 Package

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中文翻译

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NTMSD3P102R2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOT包装说明：SMALL OUTLINE, R-PDSO-G8
针数：8Reach Compliance Code：not_compliant
ECCN代码：EAR99风险等级：5.41
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：20 V
最大漏极电流 (Abs) (ID)：2.34 A最大漏极电流 (ID)：2.34 A
最大漏源导通电阻：0.085 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss)：135 pFJESD-30 代码：R-PDSO-G8
JESD-609代码：e0湿度敏感等级：1
元件数量：1端子数量：8
工作模式：ENHANCEMENT MODE最高工作温度：150 °C
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：240
极性/信道类型：P-CHANNEL最大功率耗散 (Abs)：2 W
认证状态：Not Qualified子类别：Other Transistors
表面贴装：YES端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子位置：DUAL
处于峰值回流温度下的最长时间：30晶体管应用：SWITCHING
晶体管元件材料：SILICON

NTMSD3P102R2 数据手册

 浏览型号NTMSD3P102R2的Datasheet PDF文件第2页浏览型号NTMSD3P102R2的Datasheet PDF文件第3页浏览型号NTMSD3P102R2的Datasheet PDF文件第4页浏览型号NTMSD3P102R2的Datasheet PDF文件第5页浏览型号NTMSD3P102R2的Datasheet PDF文件第6页浏览型号NTMSD3P102R2的Datasheet PDF文件第7页 
NTMSD3P102R2  
FETKY  
P−Channel Enhancement−Mode  
Power MOSFET and Schottky Diode  
Dual SO−8 Package  
Features  
• High Efficiency Components in a Single SO−8 Package  
http://onsemi.com  
• High Density Power MOSFET with Low R  
,
DS(on)  
Schottky Diode with Low V  
F
MOSFET  
−3.05 AMPERES  
−20 VOLTS  
• Independent Pin−Outs for MOSFET and Schottky Die  
Allowing for Flexibility in Application Use  
• Less Component Placement for Board Space Savings  
• SO−8 Surface Mount Package,  
0.085 W @ VGS = −10 V  
Mounting Information for SO−8 Package Provided  
Applications  
• DC−DC Converters  
• Low Voltage Motor Control  
SCHOTTKY DIODE  
1.0 AMPERES  
• Power Management in Portable and Battery−Powered Products, i.e.:  
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones  
20 VOLTS  
MOSFET MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
470 mV @ IF = 1.0 A  
J
Rating  
Symbol  
Value  
Unit  
Drain−to−Source Voltage  
V
−20  
V
V
DSS  
1
2
8
7
A
A
S
G
C
C
D
D
Gate−to−Source Voltage − Continuous  
V
"20  
GS  
8
Thermal Resistance −  
Junction−to−Ambient (Note 1.)  
Total Power Dissipation @ T = 25°C  
Continuous Drain Current @ T = 25°C  
Continuous Drain Current @ T = 70°C  
Pulsed Drain Current (Note 4.)  
R
P
I
171  
0.73  
−2.34  
−1.87  
−8.0  
°C/W  
W
A
A
A
6
θ
JA  
1
A
D
3
A
D
SO−8  
CASE 751  
STYLE 18  
4
5
I
D
A
I
DM  
TOP VIEW  
Thermal Resistance −  
Junction−to−Ambient (Note 2.)  
R
P
I
I
100  
1.25  
−3.05  
−2.44  
−12  
°C/W  
W
A
A
A
θ
JA  
MARKING DIAGRAM  
& PIN ASSIGNMENTS  
Total Power Dissipation @ T = 25°C  
A
D
Continuous Drain Current @ T = 25°C  
A
D
Continuous Drain Current @ T = 70°C  
A
D
1
2
8
7
Pulsed Drain Current (Note 4.)  
I
Anode  
Anode  
Source  
Gate  
Cathode  
Cathode  
Drain  
DM  
Thermal Resistance −  
Junction−to−Ambient (Note 3.)  
E3P102  
LYWW  
3
4
6
5
R
P
I
I
62.5  
2.0  
−3.86  
−3.10  
−15  
°C/W  
W
A
A
A
θ
JA  
Total Power Dissipation @ T = 25°C  
A
D
Drain  
Continuous Drain Current @ T = 25°C  
A
D
Continuous Drain Current @ T = 70°C  
(Top View)  
A
D
Pulsed Drain Current (Note 4.)  
I
DM  
E3P102 = Device Code  
Operating and Storage  
Temperature Range  
T , T  
−55 to  
+150  
°C  
J
stg  
L
= Assembly Location  
Y
= Year  
Single Pulse Drain−to−Source Avalanche  
E
AS  
140  
mJ  
WW  
= Work Week  
Energy − Starting T = 25°C (V  
=
J
DD  
−20 Vdc, V = −4.5 Vdc, Peak I =  
GS  
L
−7.5 Apk, L = 5 mH, R = 25 Ω)  
G
ORDERING INFORMATION  
Maximum Lead Temperature for Soldering  
T
L
260  
°C  
†
Device  
Package  
Shipping  
2500/Tape & Reel  
Purposes, 1/8″ from case for 10 seconds  
1. Minimum FR−4 or G−10 PCB, Steady State.  
2. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided),  
Steady State.  
3. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided),  
t ≤ 10 seconds.  
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.  
NTMSD3P102R2  
SO−8  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
Semiconductor Components Industries, LLC, 2003  
1
Publication Order Number:  
December, 2003 − Rev. 1  
NTMSD3P102R2/D  
 
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