5秒后页面跳转
捷配首页

Datasheet > 晶体管 > 小信号场效应晶体管> NTMSD3P102R2
NTMSD3P102R2 PDF预览

NTMSD3P102R2

更新时间： 2024-02-24 00:05:36
品牌 Logo 应用领域
安森美 - ONSEMI 肖特基二极管
页数 文件大小 规格书
10页 123K
描述
P−Channel Enhancement−Mode Power MOSFET and Schottky Diode Dual SO−8 Package

阅读下载

中文翻译

获取价格

NTMSD3P102R2 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOT
包装说明：LEAD FREE, CASE 751-07, SOP-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
风险等级：5.32配置：SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：20 V最大漏极电流 (Abs) (ID)：2.34 A
最大漏极电流 (ID)：2.34 A最大漏源导通电阻：0.085 Ω
FET 技术：METAL-OXIDE SEMICONDUCTOR最大反馈电容 (Crss)：135 pF
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
湿度敏感等级：3元件数量：1
端子数量：8工作模式：ENHANCEMENT MODE
最高工作温度：150 °C封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED极性/信道类型：P-CHANNEL
最大功率耗散 (Abs)：2 W认证状态：Not Qualified
子类别：Other Transistors表面贴装：YES
端子面层：Tin (Sn)端子形式：GULL WING
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

NTMSD3P102R2 数据手册

 浏览型号NTMSD3P102R2的Datasheet PDF文件第2页浏览型号NTMSD3P102R2的Datasheet PDF文件第3页浏览型号NTMSD3P102R2的Datasheet PDF文件第4页浏览型号NTMSD3P102R2的Datasheet PDF文件第5页浏览型号NTMSD3P102R2的Datasheet PDF文件第6页浏览型号NTMSD3P102R2的Datasheet PDF文件第7页 
NTMSD3P102R2  
FETKY  
P−Channel Enhancement−Mode  
Power MOSFET and Schottky Diode  
Dual SO−8 Package  
Features  
• High Efficiency Components in a Single SO−8 Package  
http://onsemi.com  
• High Density Power MOSFET with Low R  
,
DS(on)  
Schottky Diode with Low V  
F
MOSFET  
−3.05 AMPERES  
−20 VOLTS  
• Independent Pin−Outs for MOSFET and Schottky Die  
Allowing for Flexibility in Application Use  
• Less Component Placement for Board Space Savings  
• SO−8 Surface Mount Package,  
0.085 W @ VGS = −10 V  
Mounting Information for SO−8 Package Provided  
Applications  
• DC−DC Converters  
• Low Voltage Motor Control  
SCHOTTKY DIODE  
1.0 AMPERES  
• Power Management in Portable and Battery−Powered Products, i.e.:  
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones  
20 VOLTS  
MOSFET MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
470 mV @ IF = 1.0 A  
J
Rating  
Symbol  
Value  
Unit  
Drain−to−Source Voltage  
V
−20  
V
V
DSS  
1
2
8
7
A
A
S
G
C
C
D
D
Gate−to−Source Voltage − Continuous  
V
"20  
GS  
8
Thermal Resistance −  
Junction−to−Ambient (Note 1.)  
Total Power Dissipation @ T = 25°C  
Continuous Drain Current @ T = 25°C  
Continuous Drain Current @ T = 70°C  
Pulsed Drain Current (Note 4.)  
R
P
I
171  
0.73  
−2.34  
−1.87  
−8.0  
°C/W  
W
A
A
A
6
θ
JA  
1
A
D
3
A
D
SO−8  
CASE 751  
STYLE 18  
4
5
I
D
A
I
DM  
TOP VIEW  
Thermal Resistance −  
Junction−to−Ambient (Note 2.)  
R
P
I
I
100  
1.25  
−3.05  
−2.44  
−12  
°C/W  
W
A
A
A
θ
JA  
MARKING DIAGRAM  
& PIN ASSIGNMENTS  
Total Power Dissipation @ T = 25°C  
A
D
Continuous Drain Current @ T = 25°C  
A
D
Continuous Drain Current @ T = 70°C  
A
D
1
2
8
7
Pulsed Drain Current (Note 4.)  
I
Anode  
Anode  
Source  
Gate  
Cathode  
Cathode  
Drain  
DM  
Thermal Resistance −  
Junction−to−Ambient (Note 3.)  
E3P102  
LYWW  
3
4
6
5
R
P
I
I
62.5  
2.0  
−3.86  
−3.10  
−15  
°C/W  
W
A
A
A
θ
JA  
Total Power Dissipation @ T = 25°C  
A
D
Drain  
Continuous Drain Current @ T = 25°C  
A
D
Continuous Drain Current @ T = 70°C  
(Top View)  
A
D
Pulsed Drain Current (Note 4.)  
I
DM  
E3P102 = Device Code  
Operating and Storage  
Temperature Range  
T , T  
−55 to  
+150  
°C  
J
stg  
L
= Assembly Location  
Y
= Year  
Single Pulse Drain−to−Source Avalanche  
E
AS  
140  
mJ  
WW  
= Work Week  
Energy − Starting T = 25°C (V  
=
J
DD  
−20 Vdc, V = −4.5 Vdc, Peak I =  
GS  
L
−7.5 Apk, L = 5 mH, R = 25 Ω)  
G
ORDERING INFORMATION  
Maximum Lead Temperature for Soldering  
T
L
260  
°C  
†
Device  
Package  
Shipping  
2500/Tape & Reel  
Purposes, 1/8″ from case for 10 seconds  
1. Minimum FR−4 or G−10 PCB, Steady State.  
2. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided),  
Steady State.  
3. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided),  
t ≤ 10 seconds.  
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.  
NTMSD3P102R2  
SO−8  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
Semiconductor Components Industries, LLC, 2003  
1
Publication Order Number:  
December, 2003 − Rev. 1  
NTMSD3P102R2/D  
 
1234567...10

中文翻译

下载PDF

与NTMSD3P102R2相关器件

型号 品牌 获取价格 描述 数据表
NTMSD3P102R2/D ETC

获取价格

 		FETKY?
NTMSD3P102R2_06 ONSEMI

获取价格

 		P-Channel Enhancement-Mode Power MOSFET and Schottky Diode Dual Dual SO-8 Package
NTMSD3P102R2G ONSEMI

获取价格

 		P-Channel Enhancement-Mode Power MOSFET and Schottky Diode Dual Dual SO-8 Package
NTMSD3P102R2SG ONSEMI

获取价格

 		P-Channel Enhancement-Mode Power MOSFET and Schottky Diode Dual Dual SO-8 Package
NTMSD3P303 ONSEMI

获取价格

 		Typical Uses for FETKY Devices
NTMSD3P303R2 ONSEMI

获取价格

 		P−Channel Enhancement−Mode Power MOSFET and Schottky Diode Dual SO−8 Pac
NTMSD3P303R2/D ETC

获取价格

 		FETKY?
NTMSD3P303R2_06 ONSEMI

获取价格

 		P-Channel Enhancement-Mode Power MOSFET and Schottky Diode Dual SO-8 Package
NTMSD3P303R2G ONSEMI

获取价格

 		P-Channel Enhancement-Mode Power MOSFET and Schottky Diode Dual SO-8 Package
NTMSD6N303 ONSEMI

获取价格

 		Typical Uses for FETKY Devices

与NTMSD3P102R2相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证