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NLV14093BDTR2G PDF预览

NLV14093BDTR2G

更新时间: 2024-11-24 01:11:43
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 141K
描述
Quad 2-Input "NAND"

NLV14093BDTR2G 数据手册

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MC14093B  
Quad 2-Input “NAND"  
Schmitt Trigger  
The MC14093B Schmitt trigger is constructed with MOS  
P−channel and N−channel enhancement mode devices in a single  
monolithic structure. These devices find primary use where low power  
dissipation and/or high noise immunity is desired. The MC14093B  
may be used in place of the MC14011B quad 2−input NAND gate for  
enhanced noise immunity or to “square up” slowly changing  
waveforms.  
http://onsemi.com  
Features  
SOIC−14  
D SUFFIX  
CASE 751A  
SOEIAJ−14  
F SUFFIX  
CASE 965  
TSSOP−14  
DT SUFFIX  
CASE 948G  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Capable of Driving Two Low−Power TTL Loads or One  
Low−Power Schottky TTL Load Over the Rated Temperature  
Range  
PIN ASSIGNMENT  
IN 1  
1
2
3
4
5
6
7
14  
V
DD  
Triple Diode Protection on All Inputs  
Pin−for−Pin Compatible with CD4093  
Can be Used to Replace MC14011B  
Independent Schmitt−Trigger at each Input  
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
A
IN 2  
OUT  
13 IN 2  
12 IN 1  
A
D
D
A
OUT  
IN 1  
IN 2  
11 OUT  
10 OUT  
B
D
C
B
B
9
8
IN 2  
C
V
SS  
IN 1C  
These Devices are Pb−Free and are RoHS Compliant  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
MARKING DIAGRAMS  
Symbol  
Parameter  
Value  
Unit  
V
14  
14  
1
V
DD  
DC Supply Voltage Range  
0.5 to +18.0  
14093BG  
AWLYWW  
MC14093B  
ALYWG  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
0.5 to V + 0.5  
V
DD  
1
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
SOIC−14  
SOEIAJ−14  
14  
1
P
Power Dissipation,  
per Package (Note 1)  
500  
mW  
D
14  
093B  
ALYW G  
G
T
A
Ambient Temperature Range  
Storage Temperature Range  
55 to +125  
65 to +150  
260  
°C  
°C  
°C  
T
stg  
T
Lead Temperature  
(8−Second Soldering)  
L
TSSOP−14  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
WW, W = Work Week  
G or G  
= Pb−Free Package  
(Note: Microdot may be in either location)  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V (V or V ) V .  
ORDERING INFORMATION  
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
August, 2014 − Rev. 10  
MC14093B/D  
 

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