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NLV14504BDG PDF预览

NLV14504BDG

更新时间： 2024-11-07 01:08:43
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管接口集成电路锁存器
页数 文件大小 规格书
7页 121K
描述
Hex Level Shifter for TTL to CMOS

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NLV14504BDG 技术参数

是否无铅： 不含铅生命周期：Active
包装说明：SOP, SOP16,.25针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.03最大延迟：550 ns
输入特性：STANDARD接口集成电路类型：TTL/CMOS TO CMOS TRANSLATOR
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：9.9 mm湿度敏感等级：1
位数：1功能数量：6
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出锁存器或寄存器：NONE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
认证状态：Not Qualified筛选级别：AEC-Q100
座面最大高度：1.75 mm最大压摆率：6 mA
最大供电电压：18 V最小供电电压：3 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：3.9 mmBase Number Matches：1

NLV14504BDG 数据手册

 浏览型号NLV14504BDG的Datasheet PDF文件第2页浏览型号NLV14504BDG的Datasheet PDF文件第3页浏览型号NLV14504BDG的Datasheet PDF文件第4页浏览型号NLV14504BDG的Datasheet PDF文件第5页浏览型号NLV14504BDG的Datasheet PDF文件第6页浏览型号NLV14504BDG的Datasheet PDF文件第7页 
MC14504B  
Hex Level Shifter for TTL to  
CMOS or CMOS to CMOS  
The MC14504B is a hex non−inverting level shifter using CMOS  
technology. The level shifter will shift a TTL signal to CMOS logic  
levels for any CMOS supply voltage between 5 and 15 volts. A control  
input also allows interface from CMOS to CMOS at one logic level to  
another logic level: Either up or down level translating is  
http://onsemi.com  
accomplished by selection of power supply levels V  
and V  
.
DD  
CC  
The V level sets the input signal levels while V selects the output  
CC  
DD  
voltage levels.  
SOIC−16  
D SUFFIX  
CASE 751B  
SOEIAJ−16  
F SUFFIX  
CASE 966  
TSSOP−16  
DT SUFFIX  
CASE 948F  
Features  
• UP Translates from a Low to a High Voltage or DOWN Translates  
from a High to a Low Voltage  
PIN ASSIGNMENT  
• Input Threshold Can Be Shifted for TTL Compatibility  
V
1
2
3
4
5
6
7
8
16  
15  
14  
V
F
CC  
DD  
• No Sequencing Required on Power Supplies or Inputs for Power Up  
A
B
C
V
out  
out  
or Power Down  
A
F
in  
in  
• 3 to 18 Vdc Operation for V and V  
13 MODE  
out  
DD  
CC  
B
12  
11  
10  
9
E
out  
E
in  
• Diode Protected Inputs to V  
in  
SS  
• Capable of Driving Two Low−Power TTL Loads or One Low−Power  
out  
C
D
D
Schottky TTL Load Over the Rated Temperature Range  
in  
out  
in  
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
SS  
MARKING DIAGRAMS  
16  
• These Devices are Pb−Free and are RoHS Compliant  
16  
14504BG  
AWLYWW  
MC14504B  
ALYWG  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage Range  
DC Supply Voltage Range  
Value  
Unit  
V
1
1
V
CC  
V
DD  
−0.5 to +18.0  
−0.5 to +18.0  
−0.5 to +18.0  
SOIC−16  
SOEIAJ−16  
V
16  
V
in  
Input Voltage Range  
(DC or Transient)  
V
14  
504B  
ALYWG  
G
V
out  
Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
DD  
1
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
mW  
TSSOP−16  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
P
D
Power Dissipation, per Package  
(Note 1)  
500  
= Year  
T
Ambient Temperature Range  
Storage Temperature Range  
−55 to +125  
−65 to +150  
260  
°C  
°C  
°C  
A
WW, W = Work Week  
T
stg  
G or G  
= Pb−Free Indicator  
T
L
Lead Temperature  
(8−Second Soldering)  
(Note: Microdot may be in either location)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be  
taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V and V  
in  
out  
should be constrained to the range V ≤ (V or V ) ≤ V .  
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
July, 2014 − Rev. 9  
MC14504B/D  
 
1234567

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NLV14504BDG 替代型号

型号 品牌 替代类型 描述 数据表
MC14504BFELG ONSEMI

完全替代

 Hex Level Shifter for TTL to CMOS
MC14504BDR2G ONSEMI

完全替代

 Hex Level Shifter for TTL to CMOS or CMOS to CMOS
MC14504BDG ONSEMI

完全替代

 Hex Level Shifter for TTL to CMOS or CMOS to CMOS

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