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NLV14538BDTR2G PDF预览

NLV14538BDTR2G

更新时间： 2024-11-05 01:04:47
品牌 Logo 应用领域
安森美 - ONSEMI 时钟光电二极管逻辑集成电路
页数 文件大小 规格书
14页 198K
描述
Dual Precision Retriggerable/Resettable Monostable Multivibrator

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中文翻译

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NLV14538BDTR2G 技术参数

是否无铅： 不含铅生命周期：Active
包装说明：ROHS COMPLIANT, TSSOP-16针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.59
系列：4000/14000/40000JESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：5 mm
逻辑集成电路类型：MONOSTABLE MULTIVIBRATOR湿度敏感等级：1
数据/时钟输入次数：2功能数量：2
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5/15 V传播延迟（tpd）：600 ns
认证状态：Not Qualified筛选级别：AEC-Q100
座面最大高度：1.2 mm子类别：Prescaler/Multivibrators
最大供电电压 (Vsup)：18 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

NLV14538BDTR2G 数据手册

 浏览型号NLV14538BDTR2G的Datasheet PDF文件第2页浏览型号NLV14538BDTR2G的Datasheet PDF文件第3页浏览型号NLV14538BDTR2G的Datasheet PDF文件第4页浏览型号NLV14538BDTR2G的Datasheet PDF文件第5页浏览型号NLV14538BDTR2G的Datasheet PDF文件第6页浏览型号NLV14538BDTR2G的Datasheet PDF文件第7页 
MC14538B  
Dual Precision  
Retriggerable/Resettable  
Monostable Multivibrator  
The MC14538B is a dual, retriggerable, resettable monostable  
multivibrator. It may be triggered from either edge of an input pulse,  
and produces an accurate output pulse over a wide range of widths, the  
duration and accuracy of which are determined by the external timing  
components, C and R . Output Pulse Width T = R @ C (secs)  
http://onsemi.com  
MARKING  
X
X
X
X
R = W  
X
DIAGRAMS  
C = Farads  
X
Features  
16  
1
PDIP−16  
P SUFFIX  
CASE 648  
MC14538BCP  
AWLYYWWG  
• Unlimited Rise and Fall Time Allowed on the A Trigger Input  
• Pulse Width Range = 10 ms to 10 s  
• Latched Trigger Inputs  
• Separate Latched Reset Inputs  
• 3.0 Vdc to 18 Vdc Operational Limits  
• Triggerable from Positive (A Input) or Negative−Going Edge (B−Input)  
• Capable of Driving Two Low−Power TTL Loads or One Low−Power  
Schottky TTL Load Over the Rated Temperature Range  
• Pin−for−pin Compatible with MC14528B and CD4528B (CD4098)  
• Use the MC54/74HC4538A for Pulse Widths Less Than 10 ms with  
Supplies Up to 6 V  
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
16  
SOIC−16  
D SUFFIX  
CASE 751B  
14538BG  
AWLYWW  
1
16  
SOIC−16WB  
DW SUFFIX  
CASE 751G  
14538BG  
AWLYYWW  
1
• These Devices are Pb−Free and are RoHS Compliant  
16  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
14  
538B  
ALYWG  
G
TSSOP−16  
DT SUFFIX  
CASE 948F  
Symbol  
Parameter  
Value  
−0.5 to +18.0  
Unit  
V
V
DD  
DC Supply Voltage Range  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
DD  
1
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
16  
SOEIAJ−16  
F SUFFIX  
CASE 966  
MC14538B  
ALYWG  
P
D
Power Dissipation, per Package  
(Note 1)  
500  
mW  
T
Operating Temperature Range  
Storage Temperature Range  
−55 to +125  
−65 to +150  
260  
°C  
°C  
°C  
A
1
T
stg  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
T
Lead Temperature  
(8−Second Soldering)  
L
= Year  
WW, W = Work Week  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. Temperature Derating:  
G or G  
= Pb−Free Indicator  
(Note: Microdot may be in either location)  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
May, 2013 − Rev. 10  
MC14538B/D  
 
1234567...14

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