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NLV14555BDR2G PDF预览

NLV14555BDR2G

更新时间： 2024-11-05 01:16:51
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
6页 110K
描述
Dual Binary to 1-of-4 Decoder/Demultiplexer

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中文翻译

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NLV14555BDR2G 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP16,.25针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：4 weeks
风险等级：5.69系列：4000/14000/40000
输入调节：STANDARDJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：9.9 mm
负载电容（CL）：50 pF逻辑集成电路类型：OTHER DECODER/DRIVER
湿度敏感等级：1功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5/15 V
Prop。Delay @ Nom-Sup：440 ns传播延迟（tpd）：440 ns
认证状态：Not Qualified筛选级别：AEC-Q100
座面最大高度：1.75 mm子类别：Decoder/Drivers
最大供电电压 (Vsup)：18 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm
Base Number Matches：1

NLV14555BDR2G 数据手册

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MC14555B, MC14556B  
Dual Binary to 1-of-4  
Decoder/Demultiplexer  
The MC14555B and MC14556B are constructed with  
complementary MOS (CMOS) enhancement mode devices. Each  
Decoder/Demultiplexer has two select inputs (A and B), an active low  
Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2,  
Q3). The MC14555B has the selected output go to the “high” state,  
and the MC14556B has the selected output go to the “low” state.  
Expanded decoding such as binary−to−hexadecimal (1−of−16), etc.,  
can be achieved by using other MC14555B or MC14556B devices.  
Applications include code conversion, address decoding, memory  
selection control, and demultiplexing (using the Enable input as a data  
input) in digital data transmission systems.  
http://onsemi.com  
1
1
SOIC−16  
D SUFFIX  
CASE 751B  
SOEIAJ−16  
F SUFFIX  
CASE 966  
Features  
PIN ASSIGNMENTS  
• Diode Protection on All Inputs  
• Active High or Active Low Outputs  
• Expandable  
E
A
1
2
3
4
5
6
7
8
16  
15  
14  
13  
V
E
A
1
2
3
4
5
6
7
8
16  
15  
14  
13  
V
A
DD  
A
DD  
E
B
E
B
A
A
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
• All Outputs Buffered  
B
A
B
B
A
A
B
A
B
B
Q0  
Q1  
Q2  
Q3  
Q0  
Q1  
Q2  
Q3  
A
A
B
B
• Capable of Driving Two Low−Power TTL Loads or One Low−Power  
Schottky TTL Load Over the Rated Temperature Range  
12 Q0  
11 Q1  
10 Q2  
12 Q0  
11 Q1  
10 Q2  
A
B
B
B
B
A
B
B
B
B
A
A
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
A
A
V
SS  
9
Q3  
V
SS  
9
Q3  
• These Devices are Pb−Free and are RoHS Compliant  
MC14555B  
MC14556B  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
MARKING DIAGRAMS  
Parameter  
Symbol  
Value  
Unit  
V
DC Supply Voltage Range  
V
DD  
−0.5 to +18.0  
16  
1455xBG  
AWLYWW  
Input or Output Voltage Range  
(DC or Transient)  
V , V  
in out  
−0.5 to V  
+ 0.5  
V
DD  
1
Input or Output Current (DC or Transient)  
per Pin  
I , I  
in out  
10  
mA  
SOIC−16  
Power Dissipation, per Package (Note 1)  
Ambient Temperature Range  
P
500  
mW  
°C  
D
16  
T
A
−55 to +125  
−65 to +150  
260  
MC1455xB  
ALYWG  
Storage Temperature Range  
T
stg  
°C  
1
Lead Temperature (8−Second Soldering)  
T
°C  
L
SOEIAJ−16  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
x
A
= 5 or 6  
= Assembly Location  
1. Temperature Derating: “D/DW” Packages: –7.0 mW/°C From 65°C To 125°C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
WL, L = Wafer Lot  
YY, Y = Year  
WW, W = Work Week  
G
= Pb−Free Package  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V ≤ (V or V ) ≤ V .  
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
ORDERING INFORMATION  
SS  
DD  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
July, 2014 − Rev. 11  
MC14555B/D  
 
123456

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