MC14569B
Programmable Divide−By−N
Dual 4−Bit Binary/BCD
Down Counter
The MC14569B is a programmable divide−by−N dual 4−bit binary
or BCD down counter constructed with MOS P−Channel and
N−Channel enhancement mode devices (complementary MOS) in a
monolithic structure.
This device has been designed for use with the MC14568B phase
comparator/counter in frequency synthesizers, phase−locked loops,
and other frequency division applications requiring low power
dissipation and/or high noise immunity.
http://onsemi.com
MARKING
DIAGRAMS
16
1
PDIP−16
P SUFFIX
CASE 648
MC14569BCP
AWLYYWW
Features
• Speed−up Circuitry for Zero Detection
• Each 4−Bit Counter Can Divide Independently in BCD or Binary Mode
• Can be Cascaded With MC14526B for Frequency Synthesizer
Applications
16
14
569B
ALYW
TSSOP−16
DT SUFFIX
CASE 948F
• All Outputs are Buffered
• Schmitt Triggered Clock Conditioning
1
• Pb−Free Packages are Available*
16
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
SOIC−16
DW SUFFIX
CASE 751G
14569B
AWLYYWW
Symbol
Parameter
Value
−0.5 to +18.0
Unit
V
V
DD
DC Supply Voltage Range
V , V
in out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V + 0.5
V
DD
1
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
P
D
Power Dissipation, per Package
(Note 1)
500
mW
WW, W = Work Week
T
Ambient Temperature Range
Storage Temperature Range
−55 to +125
−65 to +150
260
°C
°C
°C
A
T
stg
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
T
Lead Temperature
(8−Second Soldering)
L
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V v (V or V ) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
February, 2005 − Rev. 5
MC14569B/D