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NLV14536BDWG PDF预览

NLV14536BDWG

更新时间： 2024-11-27 01:11:43
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
15页 151K
描述
Programmable Timer

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中文翻译

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NLV14536BDWG 技术参数

是否无铅： 不含铅生命周期：Not Recommended
零件包装代码：SOIC包装说明：SOP,
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01Factory Lead Time：7 weeks
风险等级：5.68计数方向：UP
系列：4000/14000/40000JESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：10.3 mm
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
工作模式：SYNCHRONOUS湿度敏感等级：3
位数：4功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
传播延迟（tpd）：14000 ns筛选级别：AEC-Q100
座面最大高度：2.65 mm子类别：Counter
最大供电电压 (Vsup)：18 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.5 mmBase Number Matches：1

NLV14536BDWG 数据手册

 浏览型号NLV14536BDWG的Datasheet PDF文件第2页浏览型号NLV14536BDWG的Datasheet PDF文件第3页浏览型号NLV14536BDWG的Datasheet PDF文件第4页浏览型号NLV14536BDWG的Datasheet PDF文件第5页浏览型号NLV14536BDWG的Datasheet PDF文件第6页浏览型号NLV14536BDWG的Datasheet PDF文件第7页 
MC14536B  
Programmable Timer  
The MC14536B programmable timer is a 24−stage binary ripple  
counter with 16 stages selectable by a binary code. Provisions for an  
on−chip RC oscillator or an external clock are provided. An on−chip  
monostable circuit incorporating a pulse−type output has been  
included. By selecting the appropriate counter stage in conjunction  
with the appropriate input clock frequency, a variety of timing can be  
achieved.  
http://onsemi.com  
Features  
0
24  
• 24 Flip−Flop Stages − Will Count From 2 to 2  
1
1
1
• Last 16 Stages Selectable By Four−Bit Select Code  
• 8−Bypass Input Allows Bypassing of First Eight Stages  
• Set and Reset Inputs  
SOIC−16 WB  
DW SUFFIX  
CASE 751G  
SOEIAJ−16  
F SUFFIX  
CASE 966  
TSSOP−16  
DT SUFFIX  
CASE 948F  
• Clock Inhibit and Oscillator Inhibit Inputs  
• On−Chip RC Oscillator Provisions  
PIN ASSIGNMENT  
• On−Chip Monostable Output Provisions  
SET  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
V
DD  
• Clock Conditioning Circuit Permits Operation with Very Long Rise  
RESET  
IN 1  
MONO−IN  
and Fall Times  
OSC INH  
• Test Mode Allows Fast Test Sequence  
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
• Capable of Driving Two Low−Power TTL Loads or One Low−Power  
Schottky TTL Load over the Rated Temperature Range  
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
OUT 1  
DECODE  
OUT 2  
D
C
B
A
8−BYPASS  
CLOCK INH  
V
SS  
9
• These Devices are Pb−Free and are RoHS Compliant  
MARKING DIAGRAMS  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
16  
Rating  
Symbol  
Value  
−0.5 to +18.0  
Unit  
V
14  
14536B  
AWLYWWG  
536B  
ALYWG  
G
DC Supply Voltage Range  
V
DD  
Input or Output Voltage Range  
(DC or Transient)  
V ,  
−0.5 to V + 0.5  
V
in  
out  
DD  
V
1
1
Input or Output Current  
(DC or Transient) per Pin  
I , I  
in out  
10  
mA  
TSSOP−16  
SOIC−16 WB  
Power Dissipation per Package (Note 1)  
Ambient Temperature Range  
P
500  
mW  
°C  
D
MC14536B  
ALYWG  
T
A
−55 to +125  
−65 to +150  
260  
Storage Temperature Range  
T
stg  
°C  
1
Lead Temperature, (8−Second Soldering)  
T
°C  
L
SOEIAJ−16  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C from 65_C to 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
WW, W = Work Week  
G or G  
= Pb−Free Package  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
(Note: Microdot may be in either location)  
to the range V ≤ (V or V ) ≤ V .  
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
ORDERING INFORMATION  
SS  
DD  
See detailed ordering and shipping information in the package  
dimensions section on page 12 of this data sheet.  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
November, 2014 − Rev. 14  
MC14536B/D  
 
1234567...15

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