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NLV14094BDR2G PDF预览

NLV14094BDR2G

更新时间： 2024-11-27 01:23:27
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
9页 136K
描述
8-Stage Shift/Store Register with Three-State Outputs

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中文翻译

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NLV14094BDR2G 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP16,.25针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.64计数方向：RIGHT
系列：4000/14000/40000JESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：9.9 mm
逻辑集成电路类型：SERIAL IN PARALLEL OUT最大频率@ Nom-Sup：1250000 Hz
湿度敏感等级：1位数：8
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5/15 V传播延迟（tpd）：840 ns
认证状态：Not Qualified筛选级别：AEC-Q100
座面最大高度：1.75 mm子类别：Shift Registers
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：3.9 mm
Base Number Matches：1

NLV14094BDR2G 数据手册

 浏览型号NLV14094BDR2G的Datasheet PDF文件第2页浏览型号NLV14094BDR2G的Datasheet PDF文件第3页浏览型号NLV14094BDR2G的Datasheet PDF文件第4页浏览型号NLV14094BDR2G的Datasheet PDF文件第5页浏览型号NLV14094BDR2G的Datasheet PDF文件第6页浏览型号NLV14094BDR2G的Datasheet PDF文件第7页 
MC14094B  
8-Stage Shift/Store Register  
with Three-State Outputs  
The MC14094B combines an 8−stage shift register with a data latch  
for each stage and a 3−state output from each latch.  
Data is shifted on the positive clock transition and is shifted from the  
http://onsemi.com  
seventh stage to two serial outputs. The Q output data is for use in  
S
high−speed cascaded systems. The Q output data is shifted on the  
S
following negative clock transition for use in low−speed cascaded systems.  
Data from each stage of the shift register is latched on the negative  
transition of the strobe input. Data propagates through the latch while  
strobe is high.  
Outputs of the eight data latches are controlled by 3−state buffers which  
are placed in the high−impedance state by a logic Low on Output Enable.  
SOIC−16  
D SUFFIX  
CASE 751B  
SOEIAJ−16  
F SUFFIX  
CASE 966  
TSSOP−16  
DT SUFFIX  
CASE 948F  
MARKING DIAGRAMS  
Features  
16  
16  
16  
14  
094B  
ALYWG  
G
• 3−State Outputs  
• Capable of Driving Two Low−Power TTL Loads or One  
Low−Power Schottky TTL Load Over the Rated Temperature  
Range  
14094BG  
AWLYWW  
MC14094B  
ALYWG  
1
1
1
SOIC−16  
SOEIAJ−16  
TSSOP−16  
• Input Diode Protection  
• Data Latch  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
• Dual Outputs for Data Out on Both Positive and  
Negative Clock Transitions  
• Useful for Serial−to−Parallel Data Conversion  
• Pin−for−Pin Compatible with CD4094B  
WW, W = Work Week  
G or G  
= Pb−Free Indicator  
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
• These Devices are Pb−Free and are RoHS Compliant  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
Value  
Unit  
V
V
DD  
DC Supply Voltage Range  
−0.5 to +18.0  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
DD  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
P
T
Power Dissipation, per Package (Note 1)  
Ambient Temperature Range  
500  
mW  
°C  
D
−55 to +125  
−65 to +150  
260  
A
T
stg  
Storage Temperature Range  
°C  
T
Lead Temperature  
°C  
L
(8−Second Soldering)  
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality  
should not be assumed, damage may occur and reliability may be affected.  
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be  
taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V and V  
in  
out  
should be constrained to the range V ≤ (V or V ) ≤ V .  
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
August, 2014 − Rev. 10  
MC14094B/D  
 
1234567...9

中文翻译

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NLV14094BDR2G 替代型号

型号 品牌 替代类型 描述 数据表
MC14094BCP ONSEMI

完全替代

 8-Stage Shift/Store Register with Three-State Outputs
CD4094BCN FAIRCHILD

类似代替

 8-Bit Shift Register/Latch with 3-STATE Outputs

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