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NLV14490DWR2G PDF预览

NLV14490DWR2G

更新时间: 2024-09-17 01:10:59
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安森美 - ONSEMI /
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11页 166K
描述
Hex Contact Bounce Eliminator

NLV14490DWR2G 数据手册

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MC14490  
Hex Contact Bounce  
Eliminator  
The MC14490 is constructed with complementary MOS enhancement  
mode devices, and is used for the elimination of extraneous level changes  
that result when interfacing with mechanical contacts. The digital contact  
bounce eliminator circuit takes an input signal from a bouncing contact  
and generates a clean digital signal four clock periods after the input has  
stabilized. The bounce eliminator circuit will remove bounce on both the  
“make” and the “break” of a contact closure. The clock for operation of  
the MC14490 is derived from an internal RC oscillator which requires  
only an external capacitor to adjust for the desired operating frequency  
(bounce delay). The clock may also be driven from an external clock  
source or the oscillator of another MC14490 (see Figure 5).  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP16  
MC14490P  
P SUFFIX  
CASE 648  
AWLYYWWG  
NOTE: Immediately after powerup, the outputs of the MC14490 are in  
indeterminate states.  
1
1
16  
Features  
SOIC16  
DW SUFFIX  
CASE 751G  
Diode Protection on All Inputs  
14490  
AWLYYWWG  
Six Debouncers Per Package  
Internal Pullups on All Data Inputs  
1
1
1
Can Be Used as a Digital Integrator, System Synchronizer, or Delay Line  
Internal Oscillator (RC), or External Clock Source  
TTL Compatible Data Inputs/Outputs  
16  
SOEIAJ16  
MC14490  
ALYWG  
F SUFFIX  
CASE 966  
1
Single Line Input, Debounces Both “Make” and “Break” Contacts  
Does Not Require “Form C” (Single Pole Double Throw) Input Signal  
Cascadable for Longer Time Delays  
A
= Assembly Location  
WL, L = Wafer Lot  
YY, Y = Year  
WW, W = Work Week  
Schmitt Trigger on Clock Input (Pin 7)  
Supply Voltage Range = 3.0 V to 18 V  
G
= PbFree Package  
Chip Complexity: 546 FETs or 136.5 Equivalent Gates  
These Devices are PbFree and are RoHS Compliant  
ORDERING INFORMATION  
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AECQ100  
Qualified and PPAP Capable  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
MAXIMUM RATINGS (Voltages Referenced to V  
Parameter  
)
SS  
Symbol  
Value  
Unit  
V
DC Supply Voltage Range  
V
DD  
0.5 to +18.0  
Input or Output Voltage Range  
(DC or Transient)  
V , V  
in out  
0.5 to V  
V
DD  
+ 0.5  
Input Current (DC or Transient) per Pin  
Power Dissipation, per Package (Note 1)  
Ambient Temperature Range  
I
10  
mA  
mW  
°C  
in  
P
500  
D
T
55 to +125  
65 to +150  
260  
A
Storage Temperature Range  
T
stg  
°C  
Lead Temperature (8Second Soldering)  
T
°C  
L
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the  
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect  
device reliability.  
1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be  
taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V and V  
in  
out  
should be constrained to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
May, 2013 Rev. 10  
MC14490/D  
 

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