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NLV14503BDR2G PDF预览

NLV14503BDR2G

更新时间： 2024-11-27 11:01:43
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管逻辑集成电路总线驱动器总线收发器
页数 文件大小 规格书
8页 113K
描述
六路非反相缓冲器，3 态

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中文翻译

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NLV14503BDR2G 技术参数

是否无铅： 不含铅生命周期：Active
零件包装代码：SOIC包装说明：SOP, SOP16,.25
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01Factory Lead Time：51 weeks
风险等级：5.73控制类型：ENABLE LOW
系列：4000/14000/40000JESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：9.9 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
湿度敏感等级：1位数：4
功能数量：2端口数量：2
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5/15 VProp。Delay @ Nom-Sup：150 ns
传播延迟（tpd）：150 ns认证状态：Not Qualified
筛选级别：AEC-Q100座面最大高度：1.75 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：18 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.9 mmBase Number Matches：1

NLV14503BDR2G 数据手册

 浏览型号NLV14503BDR2G的Datasheet PDF文件第2页浏览型号NLV14503BDR2G的Datasheet PDF文件第3页浏览型号NLV14503BDR2G的Datasheet PDF文件第4页浏览型号NLV14503BDR2G的Datasheet PDF文件第5页浏览型号NLV14503BDR2G的Datasheet PDF文件第6页浏览型号NLV14503BDR2G的Datasheet PDF文件第7页 
MC14049UB  
Hex Buffers  
The MC14049UB hex inverter/buffer is constructed with MOS  
P−channel and N−channel enhancement mode devices in a single  
monolithic structure. This complementary MOS device finds primary  
use where low power dissipation and/or high noise immunity is  
desired. This device provides logic−level conversion using only one  
http://onsemi.com  
supply voltage, V . The input−signal high level (V ) can exceed the  
DD  
IH  
V
DD  
supply voltage for logic−level conversions. Two TTL/DTL  
Loads can be driven when the device is used as CMOS−to−TTL/DTL  
MARKING  
DIAGRAMS  
converters (V = 5.0 V, V v 0.4 V, I ≥ 3.2 mA). Note that pins  
DD  
OL  
OL  
13 and 16 are not connected internally on this device; consequently  
connections to these terminals will not affect circuit operation.  
16  
PDIP−16  
P SUFFIX  
CASE 648  
MC14049UBCP  
AWLYYWW  
Features  
1
• High Source and Sink Currents  
• High−to−Low Level Converter  
• Supply Voltage Range = 3.0 V to 18 V  
• Meets JEDEC UB Specifications  
• V can exceed V  
16  
SOIC−16  
D SUFFIX  
CASE 751B  
14049U  
AWLYWW  
1
IN  
DD  
• Improved ESD Protection on All Inputs  
• Pb−Free Packages are Available*  
16  
TSSOP−16  
DT SUFFIX  
CASE 948F  
14  
049U  
ALYW  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
Value  
Unit  
1
V
DC Supply Voltage Range  
−0.5 to +18.0  
−0.5 to +18.0  
V
V
DD  
16  
V
Input Voltage Range  
(DC or Transient)  
in  
SOEIAJ−16  
F SUFFIX  
CASE 966  
MC14049UB  
ALYW  
V
out  
Output Voltage Range  
(DC or Transient)  
−0.5 to V  
+0.5  
V
DD  
1
I
Input Current  
(DC or Transient) per Pin  
±10  
mA  
mA  
mW  
in  
A
= Assembly Location  
= Wafer Lot  
= Year  
I
Output Current  
(DC or Transient) per Pin  
+45  
out  
WL, L  
YY, Y  
P
Power Dissipation, per Package (Note 1)  
Plastic  
SOIC  
D
WW, W = Work Week  
825  
740  
T
Ambient Temperature Range  
−55 to +125  
−65 to +150  
260  
°C  
°C  
°C  
A
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
T
stg  
Storage Temperature Range  
T
Lead Temperature (8−Second Soldering)  
L
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits  
are exceeded, device functional operation is not implied, damage may occur  
and reliability may be affected.  
*For additional information on our Pb−Free strategy  
and soldering details, please download the  
ON Semiconductor Soldering and Mounting  
Techniques Reference Manual, SOLDERRM/D.  
1. Temperature Derating: All Packages: See Figure 4.  
This device contains circuitry to protect the inputs against damage due to high  
static voltages or electric fields referenced to the V pin, only. Extra precautions  
SS  
must be taken to avoid applications of any voltage higher than the maximum rated  
voltages to this high−impedance circuit. For proper operation, the ranges V  
v
SS  
V
in  
v 18 V and V v V v V are recommended.  
SS  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,  
either V or V ). Unused outputs must be left open.  
SS  
DD  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
December, 2004 − Rev. 6  
MC14049UB/D  
 
12345678

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