MC14174B
Hex Type D Flip−Flop
The MC14174B hex type D flip−flop is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Data on the D inputs which meets the setup time
requirements is transferred to the Q outputs on the positive edge of the
clock pulse. All six flip−flops share common clock and reset inputs.
The reset is active low, and independent of the clock.
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Features
MARKING
DIAGRAMS
• Static Operation
• All Inputs and Outputs Buffered
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
16
PDIP−16
P SUFFIX
CASE 648
MC14174BCP
AWLYYWWG
1
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Functional Equivalent to TTL 74174
1
• Pb−Free Packages are Available*
16
SOIC−16
D SUFFIX
CASE 751B
14174BG
AWLYWW
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
1
1
Parameter
Symbol
Value
Unit
V
DC Supply Voltage Range
V
DD
−0.5 to +18.0
Input or Output Voltage Range
(DC or Transient)
V , V
−0.5 to V
+ 0.5
V
in out
DD
A
= Assembly Location
WL = Wafer Lot
YY, Y = Year
WW = Work Week
Input or Output Current (DC or Transient)
per Pin
I , I
in out
10
mA
G
= Pb−Free Package
Power Dissipation, per Package (Note 1)
Ambient Temperature Range
P
500
mW
°C
D
T
A
−55 to +125
−65 to +150
260
ORDERING INFORMATION
Storage Temperature Range
°C
†
Device
Package
Shipping
Lead Temperature (8−Second Soldering)
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
MC14174BCP
PDIP−16
25 Units/Rail
25 Units/Rail
MC14174BCPG
PDIP−16
(Pb−Free)
Packages: – 7.0 mW/_C From 65_C To 125_C
MC14174BD
SOIC−16
48 Units/Rail
48 Units/Rail
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
MC14174BDG
SOIC−16
(Pb−Free)
high−impedance circuit. For proper operation, V and V should be constrained
MC14174BDR2
SOIC−16
2500/Tape & Reel
2500/Tape & Reel
in
out
to the range V v (V or V ) v V
.
SS
in
out
DD
MC14174BDR2G SOIC−16
(Pb−Free)
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 6
MC14174B/D