Datasheet > NLV14077BDR2G

NLV14077BDR2G

更新时间： 2024-11-24 01:21:11

品牌	Logo	应用领域
安森美 - ONSEMI		栅
页数	文件大小	规格书
5页	94K
描述
Quad Exclusive "OR" and "NOR" Gates

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中文翻译

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数据手册

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NLV14077BDR2G 数据手册

MC14070B, MC14077B

CMOS SSI

Quad Exclusive “OR” and “NOR” Gates

The MC14070B quad exclusive OR gate and the MC14077B quad

exclusive NOR gate are constructed with MOS P−channel and

N−channel enhancement mode devices in a single monolithic

structure. These complementary MOS logic gates find primary use

where low power dissipation and/or high noise immunity is desired.

http://onsemi.com

Features

SOIC−14

D SUFFIX

CASE 751A

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• All Outputs Buffered

• Capable of Driving Two Low−Power TTL Loads or One

Low−Power Schottky TTL Load Over the Rated Temperature

Range

PIN ASSIGNMENT

• Double Diode Protection on All Inputs

IN 1

IN 2

• MC14070B − Replacement for CD4030B and CD4070B Types

• MC14077B − Replacement for CD4077B Type

IN 2

IN 1

OUT

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

OUT

IN 1

IN 2

OUT

IN 2

• These Devices are Pb−Free and are RoHS Compliant

IN 1

MAXIMUM RATINGS (Voltages Referenced to V

)

Symbol

Parameter

Value

−0.5 to +18.0

Unit

MARKING DIAGRAM

DC Supply Voltage Range

V , V

in out

Input or Output Voltage Range

(DC or Transient)

−0.5 to V + 0.5

140xxBG

I , I

Input or Output Current

(DC or Transient) per Pin

AWLYWW

in out

Power Dissipation, per Package

(Note 1)

500

WL, L

YY, Y

= Specific Device Code

= Assembly Location

= Wafer Lot

Ambient Temperature Range

Storage Temperature Range

−55 to +125

−65 to +150

260

°C

stg

= Year

WW, W = Work Week

= Pb−Free Package

Lead Temperature

(8−Second Soldering)

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be affected.

1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, V and V should be constrained

out

to the range V ≤ (V or V ) ≤ V .

out

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either V or V ). Unused outputs must be left open.

Publication Order Number:

August, 2014 − Rev. 10

MC14070B/D

12 3 4 5

中文翻译

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