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NLV14071BDR2G PDF预览

NLV14071BDR2G

更新时间： 2024-11-24 00:47:47
品牌 Logo 应用领域
安森美 - ONSEMI 栅光电二极管逻辑集成电路触发器
页数 文件大小 规格书
11页 135K
描述
B-Suffix Series CMOS Gates

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中文翻译

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NLV14071BDR2G 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP14,.25针数：14
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.66系列：4000/14000/40000
JESD-30 代码：R-PDSO-G14JESD-609代码：e3
长度：8.65 mm负载电容（CL）：50 pF
逻辑集成电路类型：OR GATE湿度敏感等级：1
功能数量：4输入次数：2
端子数量：14最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP14,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5/15 VProp。Delay @ Nom-Sup：300 ns
传播延迟（tpd）：300 ns认证状态：Not Qualified
施密特触发器：NO筛选级别：AEC-Q100
座面最大高度：1.75 mm子类别：Gates
最大供电电压 (Vsup)：18 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm
Base Number Matches：1

NLV14071BDR2G 数据手册

 浏览型号NLV14071BDR2G的Datasheet PDF文件第2页浏览型号NLV14071BDR2G的Datasheet PDF文件第3页浏览型号NLV14071BDR2G的Datasheet PDF文件第4页浏览型号NLV14071BDR2G的Datasheet PDF文件第5页浏览型号NLV14071BDR2G的Datasheet PDF文件第6页浏览型号NLV14071BDR2G的Datasheet PDF文件第7页 
MC14001B Series  
B-Suffix Series CMOS Gates  
MC14001B, MC14011B, MC14023B,  
MC14025B, MC14071B, MC14073B,  
MC14081B, MC14082B  
The B Series logic gates are constructed with P and N channel  
enhancement mode devices in a single monolithic structure  
(Complementary MOS). Their primary use is where low power  
dissipation and/or high noise immunity is desired.  
http://onsemi.com  
Features  
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
• All Outputs Buffered  
• Capable of Driving Two Low−power TTL Loads or One Low−power  
Schottky TTL Load Over the Rated Temperature Range.  
• Double Diode Protection on All Inputs Except: Triple Diode  
Protection on MC14011B and MC14081B  
SOIC−14  
D SUFFIX  
CASE 751A  
TSSOP−14  
DT SUFFIX  
CASE 948G  
MARKING DIAGRAMS  
14  
1
14  
1
• Pin−for−Pin Replacements for Corresponding CD4000 Series  
B Suffix Devices  
14  
0xxB  
ALYWG  
G
140xxBG  
AWLYWW  
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
SOIC−14  
TSSOP−14  
• These Devices are Pb−Free and are RoHS Compliant  
xx  
A
WL, L  
YY, Y  
= Specific Device Code  
= Assembly Location  
= Wafer Lot  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
Value  
−0.5 to +18.0  
Unit  
V
= Year  
V
DD  
DC Supply Voltage Range  
WW, W = Work Week  
G or G  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
DD  
= Pb−Free Package  
(Note: Microdot may be in either location)  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
DEVICE INFORMATION  
P
Power Dissipation, per Package  
(Note 1)  
500  
mW  
D
Device  
MC14001B  
MC14011B  
Description  
T
A
Ambient Temperature Range  
Storage Temperature Range  
−55 to +125  
−65 to +150  
260  
°C  
°C  
°C  
Quad 2−Input NOR Gate  
Quad 2−Input NAND Gate  
T
stg  
T
Lead Temperature  
(8−Second Soldering)  
L
MC14023B  
MC14025B  
MC14071B  
MC14073B  
Triple 3−Input NAND Gate  
Triple 3−Input NOR Gate  
Quad 2−Input OR Gate  
Triple 3−Input AND Gate  
V
ESD  
ESD Withstand Voltage  
Human Body Model  
Machine Model  
V
> 3000  
> 300  
N/A  
Charged Device Model  
MC14081B  
MC14082B  
Quad 2−Input AND Gate  
Dual 4−Input AND Gate  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V ≤ (V or V ) ≤ V .  
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
July, 2014 − Rev. 11  
MC14001B/D  
 
1234567...11

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