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NLV14077BDG PDF预览

NLV14077BDG

更新时间： 2024-11-27 11:01:43
品牌 Logo 应用领域
安森美 - ONSEMI 栅光电二极管逻辑集成电路栅极
页数 文件大小 规格书
6页 86K
描述
Quad Exclusive NOR Gate

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NLV14077BDG 技术参数

是否无铅： 不含铅生命周期：Active
包装说明：SOP,针数：14
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：51 weeks风险等级：5.73
系列：4000/14000/40000JESD-30 代码：R-PDSO-G14
JESD-609代码：e3长度：8.65 mm
逻辑集成电路类型：XNOR GATE湿度敏感等级：1
功能数量：4输入次数：2
端子数量：14最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
传播延迟（tpd）：350 ns筛选级别：AEC-Q100
座面最大高度：1.75 mm最大供电电压 (Vsup)：18 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.9 mmBase Number Matches：1

NLV14077BDG 数据手册

 浏览型号NLV14077BDG的Datasheet PDF文件第2页浏览型号NLV14077BDG的Datasheet PDF文件第3页浏览型号NLV14077BDG的Datasheet PDF文件第4页浏览型号NLV14077BDG的Datasheet PDF文件第5页浏览型号NLV14077BDG的Datasheet PDF文件第6页 
MC14070B, MC14077B  
CMOS SSI  
Quad Exclusive “OR” and “NOR” Gates  
The MC14070B quad exclusive OR gate and the MC14077B quad  
exclusive NOR gate are constructed with MOS P−channel and  
N−channel enhancement mode devices in a single monolithic  
structure. These complementary MOS logic gates find primary use  
where low power dissipation and/or high noise immunity is desired.  
http://onsemi.com  
MARKING  
DIAGRAMS  
Features  
14  
1
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
• All Outputs Buffered  
• Capable of Driving Two Low−Power TTL Loads or One Low−Power  
Schottky TTL Load Over the Rated Temperature Range  
• Double Diode Protection on All Inputs  
PDIP−14  
P SUFFIX  
CASE 646  
MC140xxBCP  
AWLYYWW  
• MC14070B − Replacement for CD4030B and CD4070B Types  
• MC14077B − Replacement for CD4077B Type  
• Pb−Free Packages are Available*  
14  
SOIC−14  
D SUFFIX  
CASE 751A  
140xxB  
AWLYWW  
1
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
Value  
−0.5 to +18.0  
Unit  
V
14  
V
DD  
DC Supply Voltage Range  
SOEIAJ−14  
F SUFFIX  
CASE 965  
MC140xxB  
AWLYWW  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
DD  
1
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
±10  
mA  
xx  
A
WL, L  
YY, Y  
= Specific Device Code  
= Assembly Location  
= Wafer Lot  
P
Power Dissipation, per Package  
(Note 1)  
500  
mW  
D
T
A
Ambient Temperature Range  
Storage Temperature Range  
−55 to +125  
−65 to +150  
260  
°C  
°C  
°C  
= Year  
WW, W = Work Week  
T
stg  
T
Lead Temperature  
L
(8−Second Soldering)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
1. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
February, 2005 − Rev. 5  
MC14070B/D  
 
123456

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