Datasheet > MPC9330

MPC9330

更新时间： 2024-02-27 22:05:15

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟发生器
页数	文件大小	规格书
16页	218K
描述
3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR

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MPC9330 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	LQFP-32	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.81	其他特性：	CAN ALSO OPERATE AT 3.3V SUPPLY
JESD-30 代码：	S-PQFP-G32	长度：	7 mm
端子数量：	32	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	120 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装形状：	SQUARE	封装形式：	FLATPACK
主时钟/晶体标称频率：	25 MHz	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	宽度：	7 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER

MPC9330 数据手册

Order Number: MPC9330/D

Rev 1, 01/2002

SEMICONDUCTOR TECHNICAL DATA

The MPC9330 is a 3.3V or 2.5V compatible, 1:6 PLL based clock

generator targeted for high performance low-skew clock distribution in

mid-range to high-performance telecomm, networking and computing

applications. With output frequencies up to 200 MHz and output skews

3.3V/2.5V 1:6 LVCMOS

less than 150 ps the device meets the needs of the most demanding

clock applications. The MPC9330 is specified for the extended

temperature range of –40°C to +85°C.

PLL CLOCK GENERATOR

Features

• 1:6 PLL based low-voltage clock generator

• 2.5V or 3.3V power supply

• Generates clock signals up to 200 MHz

• Maximum output skew of 150 ps

• On-chip crystal oscillator clock reference

• Alternative LVCMOS PLL reference clock input

• Internal and external PLL feedback

• PLL multiplies the reference clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2,

x/3 or x/4

• Supports zero-delay operation in external feedback mode

• Synchronous output clock stop in logic low eliminates output runt pulses

• Power_down feature reduces output clock frequency

• Drives up to 12 clock lines

FA SUFFIX

32 LEAD LQFP PACKAGE

CASE 873A

• 32 lead LQFP packaging

• Ambient temperature range –40°C to +85°C

• Pin and function compatible to the MPC930

Functional Description

The MPC9330 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

MPC9330 requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback

input to close the PLL feedback path in external feedback mode. The reference clock frequency and the divider for the feedback

path determine the VCO frequency. Both must be selected to match the VCO frequency range. In external PLL feedback

configuration and with the available post-PLL dividers (divide-by-2, divide-by-4 and divide-by-6), the internal VCO of the

MPC9330 is running at either 4x, 8x, 12x, 16x or 24x of the reference clock frequency. In internal feedback configuration

(divide-by-16) the internal VCO is running 16x of the reference frequency. The frequency of the QA, QB, QC output banks is a

division of the VCO frequency and can be configured independently for each output bank using the FSELA, FSELB and FSELC

pins, respectively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3 or x/4.

The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible input as the reference clock signal. The

PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference

clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency

specification and all other PLL characteristics do not apply.

The outputs can be disabled (high-impedance) by deasserting the OE/MR pin. In the PLL configuration with external feedback

selected, deasserting OE/MR causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Asserting OE/MR

will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9330 output

clock stop control allows the outputs to start and stop synchronously in the logic low state, without the potential generation of runt

pulses.

The MPC9330 is fully 2.5V and 3.3V compatible and requires no external loop filter components. All inputs (except XTAL)

accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50

transmission lines. For series terminated transmission lines, each of the MPC9330 outputs can drive one or two traces giving the

devices an effective fanout of 1:12. The device is packaged in a 7x7 mm 32-lead LQFP package.

1. Design target, pending final characterization.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

Motorola, Inc. 2002

12 3 4 5 6 7...16

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与MPC9330相关器件

型号	品牌	获取价格	描述	数据表
MPC9330AC	NXP	获取价格	120MHz, OTHER CLOCK GENERATOR, PQFP32, LEAD FREE, LQFP-32
MPC9330FA	NXP	获取价格	IC,MISCELLANEOUS CLOCK GENERATOR,CMOS,QFP,32PIN,PLASTIC
MPC9331	MOTOROLA	获取价格	3.3 V 1:6 LVCMOS PLL Clock Generator
MPC9331AC	NXP	获取价格	9331 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9331ACR2	NXP	获取价格	9331 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9331FA	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC,
MPC9331FA	NXP	获取价格	9331 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9331FAR2	NXP	获取价格	IC,1:6 OUTPUT,CMOS,QFP,32PIN,PLASTIC
MPC9331FAR2	IDT	获取价格	PLL Based Clock Driver, 9331 Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC9350	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER

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