Datasheet > MPC932FA

MPC932FA

更新时间： 2024-11-04 19:57:31

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		PC
页数	文件大小	规格书
8页	109K
描述
PLL Based Clock Driver, MPC900 Series, 6 True Output(s), 0 Inverted Output(s), PQFP32, PLASTIC, TQFP-32

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技术参数
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MPC932FA 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	PLASTIC, TQFP-32	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.88
系列：	MPC900	输入调节：	MUX
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e0
长度：	7 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.02 A	功能数量：	1
反相输出次数：		端子数量：	32
实输出次数：	6	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP32,.35SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	传播延迟（tpd）：	0.2 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.6 ns
座面最大高度：	1.6 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7 mm	最小 fmax：	120 MHz
Base Number Matches：	1

MPC932FA 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MPC932 is a 3.3V compatible PLL based clock driver device

targetted for zero delay applications. The device provides 6 outputs for

driving clock loads plus a single dedicated PLL feedback clock output.

The dedicated feedback output gives the user six choices of input

multiplication factors: x1, x1.25, x1.5, x2, x2.5 and x3.

• 6 Low Skew Clock Outputs

• 1 Dedicated PLL Feedback Output

• Individual Output Enable Control

• Fully Integrated PLL

LOW VOLTAGE

PLL CLOCK DRIVER

• Output Frequency Up to 120MHz

• 32–Lead TQFP Packaging

• 3.3V VCC

• ±100ps Cycle–to–Cycle Jitter

The MPC932 provides individual output enable control. The enables

are synchronized to the internal clock such that upon assertion the shut

down signals will hold the clocks LOW without generating a runt pulse on

the outputs. The shut down pins provide a means of powering down

certain portions of a system or a means of disabling outputs when the full

compliment is not required for a specific design. The shut down pins will

disable the outputs when driven LOW. A common shut down pin is

provided to disable all of the outputs (except the feedback output) with a

single control signal.

FA SUFFIX

TQFP PACKAGE

CASE 873A-02

Two feedback select pins are provided to select the multiplication

factor of the PLL. The MPC932 provides six multiplication factors: x1,

x1.25, x1.5, x2, x2.5 and x3. In the x1.25 and x2.5 modes, the QFB output

will not provide a 50% duty cycle. The phase detector of the MPC932 only

monitors rising edges of its feedback signals, thus for this function a 50%

duty cycle is not required. As the QFB signal can also be used to drive

other clocks in a system it is important the user understand that the duty

cycle will not be 50%. In the x1 and x1.5 modes the QFB output will

produce 50% duty cycle signals.

The MPC932 provides two pins for use in system test and debug operations. The MR/OE input will force all of the outputs into

a high impedance state to allow for back driving the outputs during system test. In addition the PLL_EN pin allows the user to

bypass the PLL and drive the outputs directly through the Ref_CLK input. Note the Ref_CLK signal will be routed through the

dividers so that it will take several transitions on the Ref_CLK input to create a transition on the outputs.

The MPC932 is fully 3.3V compatible and requires no external loop filter components. All of the inputs are LVCMOS/LVTTL

compatible and the outputs produce rail–to–rail 3.3V swings. For series terminated applications each output can drive two series

terminated 50Ω transmission lines. For parallel terminated lines the device can drive terminations of 50Ω into VCC/2. The device

is packaged in a 32–lead TQFP package to provide the optimum combination of performance, board density and cost.

3/98

REV 1

Motorola, Inc. 1998

12 3 4 5 6 7 8

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与MPC932FA相关器件

型号	品牌	获取价格	描述	数据表
MPC932FAR2	NXP	获取价格	932 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTI
MPC932FAR2	MOTOROLA	获取价格	MPC900 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLA
MPC932PFA	MOTOROLA	获取价格	PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, TQFP-32
MPC9330	MOTOROLA	获取价格	3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR
MPC9330AC	NXP	获取价格	120MHz, OTHER CLOCK GENERATOR, PQFP32, LEAD FREE, LQFP-32
MPC9330FA	NXP	获取价格	IC,MISCELLANEOUS CLOCK GENERATOR,CMOS,QFP,32PIN,PLASTIC
MPC9331	MOTOROLA	获取价格	3.3 V 1:6 LVCMOS PLL Clock Generator
MPC9331AC	NXP	获取价格	9331 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9331ACR2	NXP	获取价格	9331 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9331FA	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC,

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