Datasheet > MPC9315FAR2

MPC9315FAR2

更新时间： 2024-11-04 19:59:07

品牌	Logo	应用领域
恩智浦 - NXP		驱动输出元件逻辑集成电路
页数	文件大小	规格书
16页	310K
描述
9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC, LQFP-32

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

MPC9315FAR2 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	QFP	包装说明：	7 X 7 MM, PLASTIC, LQFP-32
针数：	32	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	5.27
其他特性：	ALSO OPERATE AT 3.3V SUPPLY	系列：	9315
输入调节：	MUX	JESD-30 代码：	S-PQFP-G32
JESD-609代码：	e0	长度：	7 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	最大I（ol）：	0.015 A
湿度敏感等级：	2	功能数量：	1
反相输出次数：		端子数量：	32
实输出次数：	8	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP32,.35SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	峰值回流温度（摄氏度）：	220
电源：	2.5/3.3 V	Prop。Delay @ Nom-Sup：	0.15 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.12 ns
座面最大高度：	1.6 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	2.625 V	最小供电电压 (Vsup)：	2.375 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	7 mm
最小 fmax：	75 MHz	Base Number Matches：	1

MPC9315FAR2 数据手册

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC9315/D

Rev 2, 02/2002

The MPC9315 is a 2.5V and 3.3V compatible, PLL based clock

generator designed for low-skew clock distribution in low-voltage

mid-range to high-performance telecom, networking and computing

applications. The MPC9315 offers 8 low-skew outputs and 2 selectable

inputs for clock redundancy. The outputs are configurable and support

1:1, 2:1, 4:1, 1:2 and 1:4 output to input frequency ratios. In addition, a

selectable output 180° phase control supports advanced clocking

schemes with inverted clock signals. The MPC9315 is specified for the

extended temperature range of –40 to +85°C.

LOW VOLTAGE

2.5V AND 3.3V PLL

CLOCK GENERATOR

Features

• Configurable 8 outputs LVCMOS PLL clock generator

• Compatible to various microprocessor such as PowerQuicc I and II

• Wide range output clock frequency of 18.75 to 160 MHz

• 2.5V and 3.3V CMOS compatible

• Designed for mid-range to high-performance telecom, networking and

computer applications

• Fully integrated PLL supports spread spectrum clocking

• Supports applications requiring clock redundancy

• Max. output skew of 120 ps (80 ps within one bank)

• Selectable output configurations (1:1, 2:1, 4:1, 1:2, 1:4 frequency ratios)

• 2 selectable LVCMOS clock inputs

FA SUFFIX

LQFP PACKAGE

CASE 873A–02

• External PLL feedback path and selectable feedback configuration

• Tristable outputs

• 32 ld LQFP package

• Ambient operating temperature range of –40 to +85°C

Functional Description

The MPC9315 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation

requires a connection of one of the device outputs to the selected feedback (FB0 or FB1) input to close the PLL feedback path.

The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected

to match the VCO frequency range. With available output dividers of divide-by-1, divide-by-2 and divide-by-4 the internal VCO of

the MPC9315 is running at either 1x, 2x or 4x of the reference clock frequency. The frequency of the QA, QB, QC output groups is

either the equal, one half or one fourth of the selected VCO frequency and can be configured for each output bank using the

FSELA, FSELB and FSELC pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and 1:4. The

REF_SEL pin selects one of the two available LVCMOS compatible reference input (CLK0 and CLK1) supporting clock

redundant applications. The selectable feedback input pin allows the user to select different feedback configurations and input to

output frequency ratios. The MPC9315 also provides a static test mode when the PLL supply pin (V

) is pulled to logic low

CCA

state (GND). In test mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test

mode is intended for system diagnostics, test and debug purpose. This test mode is fully static and the minimum clock frequency

specification does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting

OE causes the PLL to lose lock due to no feedback signal presence at FB0 or FB1. Asserting OE will enable the outputs and

close the phase locked loop, also enabling the PLL to recover to normal operation. The MPC9315 is fully 2.5V and 3.3V

compatible and requires no external loop filter components. All inputs accept LVCMOS signals while the outputs provide

LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission

lines, each of the MPC9315 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is

packaged in a 7x7 mm 32-lead LQFP package.

The fully integrated PLL of the MPC9315 allows the low skew outputs to lock onto a clock input and distribute it with essentially

zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between

the outputs and the reference signal.

For More Information On This Product,

Motorola, Inc. 2002

Go to: www.freescale.com

12 3 4 5 6 7...16

中文翻译

下载PDF

与MPC9315FAR2相关器件

型号	品牌	获取价格	描述	数据表
MPC931FA	MOTOROLA	获取价格	LVCMOS/LVTTL SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP3
MPC931FAR2	IDT	获取价格	PLL Based Clock Driver, LVCMOS/LVTTL Series, 6 True Output(s), 0 Inverted Output(s), CMOS,
MPC932	FREESCALE	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC932	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC932FA	IDT	获取价格	PLL Based Clock Driver, 932 Series, 6 True Output(s), 0 Inverted Output(s), PQFP32, TQFP-3
MPC932FA	MOTOROLA	获取价格	PLL Based Clock Driver, MPC900 Series, 6 True Output(s), 0 Inverted Output(s), PQFP32, PLA
MPC932FAR2	NXP	获取价格	932 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTI
MPC932FAR2	MOTOROLA	获取价格	MPC900 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLA
MPC932PFA	MOTOROLA	获取价格	PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, TQFP-32
MPC9330	MOTOROLA	获取价格	3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR

与MPC9315FAR2相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

13
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

7
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

34
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

30

产品中心

服务支持

精选活动

关于我们

帮助中心

MPC9315FAR2

MPC9315FAR2 技术参数

MPC9315FAR2 数据手册

与MPC9315FAR2相关器件

与MPC9315FAR2相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MPC9315FAR2

MPC9315FAR2 技术参数

MPC9315FAR2 数据手册

与MPC9315FAR2相关器件

与MPC9315FAR2相关文章

您还可以找

您在本页遇到什么问题？