Datasheet > MPC9315

MPC9315

更新时间： 2024-11-04 20:30:03

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
19页	407K
描述
PLL Based Clock Driver

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技术参数
数据手册

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MPC9315 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.72	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
Base Number Matches：	1

MPC9315 数据手册

2.5V and 3.3V CMOS PLL

Clock Generator and Driver

MPC9315

OBSOLETE

The MPC9315 is a 2.5 V and 3.3 V compatible, PLL based clock generator

designed for low-skew clock distribution in low-voltage mid-range to

high-performance telecom, networking and computing applications. The

MPC9315 offers 8 low-skew outputs and 2 selectable inputs for clock

redundancy. The outputs are configurable and support 1:1, 2:1, 4:1, 1:2 and 1:4

output to input frequency ratios. In addition, a selectable output 180 phase

control supports advanced clocking schemes with inverted clock signals. The

MPC9315 is specified for the extended temperature range of –40 to +85C.

MPC9315

LOW VOLTAGE

2.5 V AND 3.3 V PLL

CLOCK GENERATOR

Features

•

Configurable 8 Outputs LVCMOS PLL Clock Generator

Compatible to Various Microprocessors Such As PowerQUICC I and II

Wide Range Output Clock Frequency of 18.75 to 160 MHz

2.5 V and 3.3 V CMOS Compatible

Designed for Mid-Range to High-Performance Telecom, Networking and

Computer Applications

•

Fully Integrated PLL Supports Spread Spectrum Clocking

Supports Applications Requiring Clock Redundancy

Max. Output Skew of 120 ps (80 ps Within One Bank)

Selectable Output Configurations (1:1, 2:1, 4:1, 1:2, 1:4 Frequency Ratios)

Two Selectable LVCMOS Clock Inputs

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-04

External PLL Feedback Path and Selectable Feedback Configuration

Tristable Outputs

32-Lead LQFP Package

Ambient Operating Temperature Range of -40 to +85C

32-Lead Pb-Free Package

Functional Description

The MPC9315 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation

requires a connection of one of the device outputs to the selected feedback (FB0 or FB1) input to close the PLL feedback path.

The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected

to match the VCO frequency range. With available output dividers of divide-by-1, divide-by-2 and divide-by-4, the internal VCO

of the MPC9315 is running at either 1x, 2x or 4x of the reference clock frequency. The frequency of the QA, QB, QC output groups

is either the equal, one half or one fourth of the selected VCO frequency and can be configured for each output bank using the

FSELA, FSELB and FSELC pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and 1:4. The

REF_SEL pin selects one of the two available LVCMOS compatible reference input (CLK0 and CLK1) supporting clock redundant

applications. The selectable feedback input pin allows the user to select different feedback configurations and input to output

frequency ratios. The MPC9315 also provides a static test mode when the PLL supply pin (V_CCA) is pulled to logic low state

(GND). In test mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode

is intended for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency spec-

ification does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE

causes the PLL to lose lock due to no feedback signal presence at FB0 or FB1. Asserting OE will enable the outputs and close

the phase locked loop, also enabling the PLL to recover to normal operation. The MPC9315 is fully 2.5 V and 3.3 V compatible

and requires no external loop filter components. All inputs accept LVCMOS signals while the outputs provide LVCMOS compat-

ible levels with the capability to drive terminated 50  transmission lines. For series terminated transmission lines, each of the

MPC9315 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a 7x7 mm²

32-lead LQFP package.

The fully integrated PLL of the MPC9315 allows the low skew outputs to lock onto a clock input and distribute it with essentially

zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between

the outputs and the reference signal.

Revision 6, October 4, 2016

OBSOLETE

12 3 4 5 6 7...19

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与MPC9315相关器件

型号	品牌	获取价格	描述	数据表
MPC9315AC	NXP	获取价格	9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9315FA	NXP	获取价格	9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9315FA	MOTOROLA	获取价格	2.5V and 3.3V CMOS PLL Clock Generator and Driver
MPC9315FAR2	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32
MPC9315FAR2	NXP	获取价格	9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC931FA	MOTOROLA	获取价格	LVCMOS/LVTTL SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP3
MPC931FAR2	IDT	获取价格	PLL Based Clock Driver, LVCMOS/LVTTL Series, 6 True Output(s), 0 Inverted Output(s), CMOS,
MPC932	FREESCALE	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC932	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC932FA	IDT	获取价格	PLL Based Clock Driver, 932 Series, 6 True Output(s), 0 Inverted Output(s), PQFP32, TQFP-3

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