Datasheet > MMJL-29C80FP883

MMJL-29C80FP883

更新时间： 2024-11-05 20:55:03

品牌	Logo	应用领域
TEMIC		时钟外围集成电路
页数	文件大小	规格书
18页	287K
描述
Fast Cosine Transform Processor, 12-Bit, CMOS, CQCC44, MQFP-44

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技术参数
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MMJL-29C80FP883 技术参数

生命周期：	Transferred	包装说明：	MQFP-44
Reach Compliance Code：	unknown	风险等级：	5.67
边界扫描：	NO	最大时钟频率：	20 MHz
外部数据总线宽度：	12	JESD-30 代码：	S-CQFP-G44
低功率模式：	YES	端子数量：	44
输出数据总线宽度：	12	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装形状：	SQUARE	封装形式：	FLATPACK
认证状态：	Not Qualified	筛选级别：	MIL-STD-883
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	端子形式：	GULL WING
端子位置：	QUAD	uPs/uCs/外围集成电路类型：	DSP PERIPHERAL, FAST COSINE TRANSFRM PROCESSOR
Base Number Matches：	1

MMJL-29C80FP883 数据手册

29C80F

2D Discrete Cosine Transform Circuit

Introduction

The 29C80F is a dedicated two-dimensional discrete Except for clock circuitry, the 29C80F is composed of 5

cosine transform circuit. The two-dimensional forward blocks :

transform (FDCT) or inverse transform (IDCT) is

performed on fixed 8 × 8 pixel or coefficient blocks (64

samples).

– 2 identical 1D DCT processors (line DCT and column

DCT).

– 1 memory for line/column transposition (between the 2

These blocks can be scanned from left to right, line by DCT processors).

line, or up to down, column by column, or in zig-zag order

for coefficient blocks only. If the input matrix is scanned

line by line and if the zig-zag order is not used, then the

output matrix will appear column by column

(line/column transposition between inputs and outputs).

– 1 memory for zig-zag scanning.

– 1 clipping operator (following the column DCT

processor).

All the internal sequencers are reset then started by a

pipelined signal, BLKIN (Block Input), and stopped after

a fixed number of cycles. The BLKOUT (Block Output)

signal indicates the beginning of a block on the output

data bus DO[0..11].

For FDCT, the input bus receives pixels coded with 8 or

9 bit in two’s complement format and the 29C80F output

coefficients are coded with 12 bit in two’s complement

format..

The latent period (the time between input data and its

For IDCT, the input bus receives coefficients coded with corresponding output result) is 128 CLK cycles

12 bit in two’s complement format and the 29C80F output (regardless of zig-zag scanning selection). The 29C80F

pixels are coded with 8 or 9 bit in two’s complement has been designed to process contiguous blocks.

format.

However, it is possible to introduce a gap period between

two blocks and/or to mix FDCT/IDCT by respecting

some recommendations.

A parallel architecture and a DCT based on modified

CHEN algorithm are used allowing high precision

compatible with the CCITT H261 requirements for

accuracy and fast operation up to 20 Mpixels/s.

The 29C80F is designed to cover a wide range of real time

DCT coding/decoding applications up to 20 MSamples/s.

Input Data Bus⁽¹⁾

Output Data Bus⁽¹⁾

(2)

Pixels 8-bit : DI [11..4]

FDCT

Coefficients : DO[11..0]

(3)

Pixels 9-bit : DI[11..3]

(4)

(5)

Pixels 8-bit : DI[11..4]

Pixels 9-bit : DI[11..3]

IDCT

Coefficients : DO[11..0]

Notes : 1. Data coded with 2’s complement

2. DI[3..0] must be tied to VIL

4. DO[3..0] forced to VOL

5. DO[2..0] forced to VOL

3. DI[2..0] must be tied to VIL

Features

D Forward and inverse 8 × 8 data transform

D DC to 20 MHz pixel rate (20 MHz clock)

D 9 bit two’s complement pixel format

D 8 bit two’s complement pixel format with optimised

accuracy

D 12 bit two’s complement coefficient format

D Fully compliant with CCITT H261 accuracy

D Selectable zig-zag scanning for coefficient blocks

D Full parallel architecture

D Radiation tolerant for space application

D Fully synchronous interface

D 128 block cycles latency

D Power down mode

D Tristate control output

D TTL compatible inputs and outputs

D Single 5 V ± 10 % power supply

D 44 pin MQFPJ

D Advanced 0.8 µm CMOS technology

MATRA MHS

Rev. D (25 Mar.97)

12 3 4 5 6 7...18

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