5秒后页面跳转
MC10133L PDF预览

MC10133L

更新时间: 2024-11-04 21:05:59
品牌 Logo 应用领域
安森美 - ONSEMI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
8页 125K
描述
10K SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16

MC10133L 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.59
Is Samacsys:N系列:10K
JESD-30 代码:R-GDIP-T16长度:19.495 mm
逻辑集成电路类型:D LATCH位数:2
功能数量:2端子数量:16
最高工作温度:85 °C最低工作温度:-30 °C
输出特性:OPEN-EMITTER输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
传播延迟(tpd):6 ns认证状态:Not Qualified
座面最大高度:5.08 mm表面贴装:NO
技术:ECL温度等级:OTHER
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL触发器类型:HIGH LEVEL
宽度:7.62 mmBase Number Matches:1

MC10133L 数据手册

 浏览型号MC10133L的Datasheet PDF文件第2页浏览型号MC10133L的Datasheet PDF文件第3页浏览型号MC10133L的Datasheet PDF文件第4页浏览型号MC10133L的Datasheet PDF文件第5页浏览型号MC10133L的Datasheet PDF文件第6页浏览型号MC10133L的Datasheet PDF文件第7页 
The MC10133 is a high speed, low power, quad latch consisting of  
four bistable latch circuits with D type inputs and gated Q outputs,  
allowing direct wiring to a bus. When the clock is high, outputs will  
follow D inputs. Information is latched on the negative going  
transition of the clock.  
http://onsemi.com  
The outputs are gated when the output enable (G) is low. All four  
latches may be clocked at one time with the common clock (C ), or  
each half may be clocked separately with its clock enable (CE).  
C
MARKING  
DIAGRAMS  
P =310 mW typ/pkg (No Load)  
D
16  
t = 4.0 ns typ  
pd  
CDIP–16  
L SUFFIX  
CASE 620  
MC10133L  
AWLYYWW  
t , t = 2.0 ns typ (20%–80%)  
r f  
LOGIC DIAGRAM  
1
D0  
3
Q0  
2
6
Q0  
Q1  
16  
PDIP–16  
P SUFFIX  
CASE 648  
MC10133P  
AWLYYWW  
G0  
D1  
5
7
Q1  
Q2  
1
CE  
4
1
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
V
CC2  
C
C
13  
PLCC–20  
FN SUFFIX  
CASE 775  
V
EE  
10133  
CE 12  
AWLYYWW  
D2  
G1 10  
9
11 Q2  
15 Q3  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
D3 14  
Q3  
WW = Work Week  
DIP PIN ASSIGNMENT  
TRUTH TABLE  
V
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
G
C
D
Q
n+1  
Q3  
D3  
Q0  
H
L
L
L
X
L
H
H
X
X
L
L
Q
L
n
D
0
H
H
C
C
CE  
G0  
Q1  
C = C = CE  
C
CE  
Q2  
G1  
D2  
ORDERING INFORMATION  
D1  
Device  
Package  
Shipping  
V
EE  
MC10133L  
CDIP–16  
25 Units / Rail  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion Tables on page 18  
of the ON Semiconductor MECL Data Book (DL122/D).  
MC10133P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
MC10133FN  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 7  
MC10133/D  

MC10133L 替代型号

型号 品牌 替代类型 描述 数据表
MC10H131FNR2 ONSEMI

功能相似

Dual D Type Master−Slave Flip−Flop
MC10H131FN ONSEMI

功能相似

Dual D Type Master−Slave Flip−Flop
MC10186L ONSEMI

功能相似

Hex D Master-Slave Flip-Flop with Reset

与MC10133L相关器件

型号 品牌 获取价格 描述 数据表
MC10133LD MOTOROLA

获取价格

暂无描述
MC10133LDS MOTOROLA

获取价格

D Latch, 2-Func, 2-Bit, ECL10K, CDIP16
MC10133LS MOTOROLA

获取价格

D Latch, 2-Func, 2-Bit, ECL10K, CDIP16
MC10133P MOTOROLA

获取价格

Quad Latch
MC10133P ONSEMI

获取价格

10K SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP16, PLASTIC, DIP-16
MC10133PD MOTOROLA

获取价格

暂无描述
MC10133PDS MOTOROLA

获取价格

D Latch, 2-Func, 2-Bit, ECL10K, PDIP16
MC10133PS MOTOROLA

获取价格

暂无描述
MC10134 MOTOROLA

获取价格

DUAL MULTIPLEXER WITH LATCH
MC10134FN MOTOROLA

获取价格

Dual Multiplexer With Latch