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MC10133PD PDF预览

MC10133PD

更新时间: 2024-11-04 13:00:31
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
4页 89K
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MC10133PD 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10133 is a high speed, low power, quad latch consisting of four  
bistable latch circuits with D type inputs and gated Q outputs, allowing direct  
wiring to a bus. When the clock is high, outputs will follow D inputs. Information  
is latched on the negative going transition of the clock.  
The outputs are gated when the output enable (G) is low. All four latches may  
be clocked at one time with the common clock (C ), or each half may be  
C
clocked separately with its clock enable (CE).  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P
= 310 mW typ/pkg (No Load)  
= 4.0 ns typ  
D
t
pd  
t , t = 2.0 ns typ (20%–80%)  
r f  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
LOGIC DIAGRAM  
D0  
3
Q0  
2
6
Q0  
Q1  
DIP  
PIN ASSIGNMENT  
G0  
D1  
5
7
Q1  
CE  
4
V
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
C
C
13  
Q3  
D3  
Q0  
CE 12  
D
0
D2  
9
Q2  
Q3  
C
C
CE  
G0  
Q1  
11 Q2  
15 Q3  
G1 10  
CE  
Q2  
G1  
D2  
D3 14  
D1  
TRUTH TABLE  
V
EE  
G
C
D
Q
n+1  
L
V
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
CC2  
EE  
H
L
L
L
X
L
H
H
X
X
L
Q
n
L
H
H
C = C + CE  
C
9/96  
Motorola, Inc. 1996  
REV 6  

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