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MC10135_02 PDF预览

MC10135_02

更新时间: 2024-11-04 04:59:43
品牌 Logo 应用领域
安森美 - ONSEMI 触发器
页数 文件大小 规格书
8页 112K
描述
Dual J-K Master-Slave Flip-Flop

MC10135_02 数据手册

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MC10135  
Dual J-K Master-Slave  
Flip-Flop  
The MC10135 is a dual master–slave dc coupled J–K flip–flop.  
Asynchro– nous set (S) and reset (R) are provided. The set and reset  
inputs override the clock.  
A common clock is provided with separate J–K inputs. When the  
clock is static, the J–K inputs do not effect the output.  
The output states of the flip–flop change on the positive transition of  
the clock.  
http://onsemi.com  
MARKING  
DIAGRAMS  
P = 280 mW typ/pkg (No Load)  
16  
D
CDIP–16  
L SUFFIX  
CASE 620  
f = 140 MHz typ  
Tog  
MC10135L  
AWLYYWW  
t = 3.0 ns typ  
pd  
t , t = 2.5 ns typ (20%–80%)  
r
f
1
16  
LOGIC DIAGRAM  
DIP PIN ASSIGNMENT  
S1  
5
PDIP–16  
P SUFFIX  
CASE 648  
MC10135P  
AWLYYWW  
V
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
2
3
Q1  
Q1  
J1  
7
6
Q2  
Q2  
R2  
S2  
K2  
J2  
Q1  
1
K1  
1
Q1  
R1  
S1  
K1  
J1  
R1  
C
4
9
PLCC–20  
FN SUFFIX  
CASE 775  
10135  
S2 12  
AWLYYWW  
15  
14  
Q2  
2  
J2 10  
K2  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
V
C
EE  
V
PIN 1  
= PIN 16  
= PIN 8  
CC1  
CC2  
Pin assignment is for Dual–in–Line Packae.  
For PLCC pin assignment, see the Pin Con
Tables on page 18 of the ON Semiconductor
Data Book (DL122/D).  
V
EE  
ORDERING INFORMATION  
Device  
Package  
Shipping  
R–S TRUTH TABLE  
CLOCK J–K TRUTH TABLE*  
MC10135L  
CDIP–16  
25 Units / Rail  
R
S
Q
J
K
Q
n+1  
n+1  
MC10135P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
L
L
H
H
L
H
L
Q
H
L
H
L
L
L
H
H
Q
n
L
H
Q
n
n
MC10135FN  
L
H
N.D.  
H
N.D. = Not Defined  
*Output states change on positive  
transition of clock for J–K input  
condition present.  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
January, 2002 – Rev. 7  
MC10135/D  

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