MC10135

更新时间： 2024-11-03 22:54:59

品牌	Logo	应用领域
安森美 - ONSEMI		触发器
页数	文件大小	规格书
5页	114K
描述
Dual J-K Master-Slave Flip-Flop

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数据手册

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MC10135 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10135 is a dual master–slave dc coupled J–K flip–flop. Asynchro–

nous set (S) and reset (R) are provided. The set and reset inputs override the

clock.

A common clock is provided with separate J–K inputs. When the clock is

static, the J–K inputs do not effect the output.

The output states of the flip–flop change on the positive transition of the

clock.

L SUFFIX

CERAMIC PACKAGE

CASE 620–10

P SUFFIX

PLASTIC PACKAGE

CASE 648–08

= 280 mW typ/pkg (No Load)

= 140 MHz typ

= 3.0 ns typ

Tog

FN SUFFIX

PLCC

CASE 775–02

t , t = 2.5 ns typ (20%–80%)

r f

DIP

PIN ASSIGNMENT

LOGIC DIAGRAM

CC2

CC1

= PIN 1

= PIN 16

= PIN 8

CC1

CC2

S2 12

J2 10

K2 11

R2 13

Pin assignment is for Dual–in–Line Package.

For PLCC pin assignment, see the Pin Conversion

Tables on page 6–11 of the Motorola MECL Data

Book (DL122/D).

R–S TRUTH TABLE

CLOCK J–K TRUTH TABLE*

n+1

N.D.

N.D. = Not Defined

*Output states change on positive

transition of clock for J–K input

condition present.

3/93

Motorola, Inc. 1996

REV 5

3–22

12 3 4 5

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与MC10135相关器件

型号	品牌	获取价格	描述	数据表
MC10135_02	ONSEMI	获取价格	Dual J-K Master-Slave Flip-Flop
MC10135FN	ONSEMI	获取价格	Dual J-K Master-Slave Flip-Flop
MC10135FN	MOTOROLA	获取价格	Dual J-K Master-Slave Flip-Flop
MC10135FNR2	MOTOROLA	获取价格	10K SERIES, POSITIVE EDGE TRIGGERED JBAR-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC20, PLA
MC10135FNR2	ONSEMI	获取价格	10K SERIES, POSITIVE EDGE TRIGGERED JBAR-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC20, PLA
MC10135L	MOTOROLA	获取价格	Dual J-K Master-Slave Flip-Flop
MC10135L	ONSEMI	获取价格	Dual J-K Master-Slave Flip-Flop
MC10135LD	MOTOROLA	获取价格	J-K Flip-Flop, 2-Func, Master-slave Triggered, ECL, CDIP16
MC10135LDS	MOTOROLA	获取价格	J-K Flip-Flop, 2-Func, Master-slave Triggered, ECL, CDIP16
MC10135LS	MOTOROLA	获取价格	J-K Flip-Flop, 2-Func, Master-slave Triggered, ECL, CDIP16